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Differential D134266 Diff 462394 llvm/include/llvm/CodeGen/TargetInstrInfo.h

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llvm/include/llvm/CodeGen/TargetInstrInfo.h

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TargetInstrInfo(const TargetInstrInfo &) = delete;		TargetInstrInfo(const TargetInstrInfo &) = delete;
TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;		TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
virtual ~TargetInstrInfo();		virtual ~TargetInstrInfo();

static bool isGenericOpcode(unsigned Opc) {		static bool isGenericOpcode(unsigned Opc) {
return Opc <= TargetOpcode::GENERIC_OP_END;		return Opc <= TargetOpcode::GENERIC_OP_END;
}		}

		static bool isGenericAtomicRMWOpcode(unsigned Opc) {
		return Opc >= TargetOpcode::GENERIC_ATOMICRMW_OP_START &&
		arsenmUnsubmitted Not Done Reply Inline Actions Opc >= START? arsenm: Opc >= START?
		Opc <= TargetOpcode::GENERIC_ATOMICRMW_OP_END;
		}

/// Given a machine instruction descriptor, returns the register		/// Given a machine instruction descriptor, returns the register
/// class constraint for OpNum, or NULL.		/// class constraint for OpNum, or NULL.
virtual		virtual
const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,		const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
		arsenmUnsubmitted Not Done Reply Inline Actions I think the benefit of this one is dubious. They don't have the same operand structure arsenm: I think the benefit of this one is dubious. They don't have the same operand structure
		yassinghAuthorUnsubmitted Done Reply Inline Actions We need this to check divergence of an instruction in GMIR, it was either this or moving this opcode matching inside isDivergent type function which didn't look right and also wasn't consistent with how Atomic instructions are handled in IR divergence/uniformity analysis. yassingh: We need this to check divergence of an instruction in GMIR, it was either this or moving this…
		arsenmUnsubmitted Not Done Reply Inline Actions There's nothing wrong with just checking opcodes where you need to. The IR and MIR aren't structured exactly the same way arsenm: There's nothing wrong with just checking opcodes where you need to. The IR and MIR aren't…
		yassinghAuthorUnsubmitted Done Reply Inline Actions There's nothing wrong with just checking opcodes where you need to. The IR and MIR aren't structured exactly the same way Okay. I'll get rid of the second predicate, maybe when the divergence revision comes up we can revisit this if that doesn't look right yassingh: > There's nothing wrong with just checking opcodes where you need to. The IR and MIR aren't…
const TargetRegisterInfo *TRI,		const TargetRegisterInfo *TRI,
const MachineFunction &MF) const;		const MachineFunction &MF) const;

/// Return true if the instruction is trivially rematerializable, meaning it		/// Return true if the instruction is trivially rematerializable, meaning it
/// has no side effects and requires no operands that aren't always available.		/// has no side effects and requires no operands that aren't always available.
/// This means the only allowed uses are constants and unallocatable physical		/// This means the only allowed uses are constants and unallocatable physical
/// registers so that the instructions result is independent of the place		/// registers so that the instructions result is independent of the place
/// in the function.		/// in the function.
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