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llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
| Show All 10 Lines | |||||
| // SiFive7 machine model for scheduling and other instruction cost heuristics. | // SiFive7 machine model for scheduling and other instruction cost heuristics. | ||||
| def SiFive7Model : SchedMachineModel { | def SiFive7Model : SchedMachineModel { | ||||
| let MicroOpBufferSize = 0; // Explicitly set to zero since SiFive7 is in-order. | let MicroOpBufferSize = 0; // Explicitly set to zero since SiFive7 is in-order. | ||||
| let IssueWidth = 2; // 2 micro-ops are dispatched per cycle. | let IssueWidth = 2; // 2 micro-ops are dispatched per cycle. | ||||
| let LoadLatency = 3; | let LoadLatency = 3; | ||||
| let MispredictPenalty = 3; | let MispredictPenalty = 3; | ||||
| let CompleteModel = 0; | let CompleteModel = 0; | ||||
| let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx, | let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx, | ||||
| HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, | HasStdExtZcmt, HasStdExtZknd, HasStdExtZkne, | ||||
| HasStdExtZksed, HasStdExtZksh, HasStdExtZkr, | HasStdExtZknh, HasStdExtZksed, HasStdExtZksh, | ||||
| HasVInstructions]; | HasStdExtZkr, HasVInstructions]; | ||||
| } | } | ||||
| // The SiFive7 microarchitecture has two pipelines: A and B. | // The SiFive7 microarchitecture has two pipelines: A and B. | ||||
| // Pipe A can handle memory, integer alu and vector operations. | // Pipe A can handle memory, integer alu and vector operations. | ||||
| // Pipe B can handle integer alu, control flow, integer multiply and divide, | // Pipe B can handle integer alu, control flow, integer multiply and divide, | ||||
| // and floating point computation. | // and floating point computation. | ||||
| let SchedModel = SiFive7Model in { | let SchedModel = SiFive7Model in { | ||||
| let BufferSize = 0 in { | let BufferSize = 0 in { | ||||
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