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llvm/lib/Target/RISCV/RISCVSchedRocket.td
| Show All 12 Lines | |||||
| // Rocket machine model for scheduling and other instruction cost heuristics. | // Rocket machine model for scheduling and other instruction cost heuristics. | ||||
| def RocketModel : SchedMachineModel { | def RocketModel : SchedMachineModel { | ||||
| let MicroOpBufferSize = 0; // Rocket is in-order. | let MicroOpBufferSize = 0; // Rocket is in-order. | ||||
| let IssueWidth = 1; // 1 micro-op is dispatched per cycle. | let IssueWidth = 1; // 1 micro-op is dispatched per cycle. | ||||
| let LoadLatency = 3; | let LoadLatency = 3; | ||||
| let MispredictPenalty = 3; | let MispredictPenalty = 3; | ||||
| let CompleteModel = false; | let CompleteModel = false; | ||||
| let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx, | let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx, | ||||
| HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, | HasStdExtZcmt, HasStdExtZknd, HasStdExtZkne, | ||||
| HasStdExtZksed, HasStdExtZksh, HasStdExtZkr, | HasStdExtZknh, HasStdExtZksed, HasStdExtZksh, | ||||
| HasVInstructions, HasVInstructionsI64]; | HasStdExtZkr, HasVInstructions, HasVInstructionsI64]; | ||||
| } | } | ||||
| //===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
| // Define each kind of processor resource and number available. | // Define each kind of processor resource and number available. | ||||
| // Modeling each pipeline as a ProcResource using the BufferSize = 0 since | // Modeling each pipeline as a ProcResource using the BufferSize = 0 since | ||||
| // Rocket is in-order. | // Rocket is in-order. | ||||
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