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Differential D133863 Diff 460266 llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

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llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

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//===-- RISCVInstrInfoZc.td - RISC-V 'Zc' instructions -----*- tablegen -*-===//
//
reamesUnsubmitted
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We have Zca in RISCVInstrInfoC.td. Not sure it makes sense to have Zcmt in one place, and Zca in another.

Also, did Zca change between 0.7 and 0.7.5? If so, any plans to update that extension?

reames: We have Zca in RISCVInstrInfoC.td. Not sure it makes sense to have Zcmt in one place, and Zca…
craig.topperUnsubmitted
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I think all Zc* should be in RISCVInstrInfoC.td. Zca/Zcf/Zcd already have to be in that file. Might as well put the rest there.

We should mention the Zc* extensions in the header of that file.

craig.topper: I think all Zc* should be in RISCVInstrInfoC.td. Zca/Zcf/Zcd already have to be in that file.
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
///
/// This file describes the RISC-V instructions from the 'Zc' Code-size
/// reduction extension, version 0.70.5.
/// This version is still experimental as the 'Zc' extension hasn't been
reamesUnsubmitted
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It's not just one extension. It is several sub-extensions.

Please reword as "from the Zc* family of code size reduction extensions, version ...

reames: It's not just one extension. It is several sub-extensions. Please reword as "from the Zc*…
/// ratified yet.
///
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Operand and SDNode transformation definitions.
//===----------------------------------------------------------------------===//
def uimm6 : Operand<XLenVT>,
jrtc27Unsubmitted
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Blank line

jrtc27: Blank line
ImmLeaf<XLenVT, [{return isUInt<6>(Imm);}]> {
jrtc27Unsubmitted
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This should line up?

jrtc27: This should line up?
let ParserMatchClass = UImmAsmOperand<6>;
let EncoderMethod = "getImmOpValue";
let DecoderMethod = "decodeUImmOperand<6>";
let MCOperandPredicate = [{
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
return false;
return MCOp.isBareSymbolRef();
jrtc27Unsubmitted
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I don't think we want this? cm.jt sym isn't a meaningful thing.

jrtc27: I don't think we want this? `cm.jt sym` isn't a meaningful thing.
}];
}
def uimm8 : Operand<XLenVT>,
ImmLeaf<XLenVT, [{return isUInt<8>(Imm);}]> {
let ParserMatchClass = UImmAsmOperand<8>;
let EncoderMethod = "getImmOpValue";
let DecoderMethod = "decodeUImmOperand<8>";
let MCOperandPredicate = [{
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
return false;
return MCOp.isBareSymbolRef();
}];
}
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
let Predicates = [HasStdExtZcmt],
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
def CM_JT : RVInst16CJ<0b101, 0b10, (outs), (ins uimm6:$index),
"cm.jt", "$index">{
bits<6> index;
let Inst{12-8} = 0b00000;
let Inst{7-2} = index;
}
def CM_JALT : RVInst16CJ<0b101, 0b10, (outs), (ins uimm8:$index),
"cm.jalt", "$index">{
bits<8> index;
let Inst{12-10} = 0b000;
let Inst{9-2} = index;
}
}
craig.topperUnsubmitted
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Indent 1 more space

craig.topper: Indent 1 more space