Differential D132436 Diff 455103 llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h

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llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h

Show First 20 Lines • Show All 481 Lines • ▼ Show 20 Lines	private:

using ReservedRegSet = SmallSetVector<Register, 8>;		using ReservedRegSet = SmallSetVector<Register, 8>;
// To track the VGPRs reserved for WWM instructions. They get stack slots		// To track the VGPRs reserved for WWM instructions. They get stack slots
// later during PrologEpilogInserter and get added into the superset WWMSpills		// later during PrologEpilogInserter and get added into the superset WWMSpills
// for actual spilling. A separate set makes the register reserved part and		// for actual spilling. A separate set makes the register reserved part and
// the serialization easier.		// the serialization easier.
ReservedRegSet WWMReservedRegs;		ReservedRegSet WWMReservedRegs;

		using CustomSGPRSpillsMap = DenseMap<Register, CustomSGPRSaveInfo>;
		// To track the custom SGPR spill method used for a CSR SGPR register during
		// frame lowering. Even though the SGPR spills are handled during
		// SILowerSGPRSpills pass, some special handling needed later during the
		// PrologEpilogInserter.
		CustomSGPRSpillsMap CustomSGPRSpills;

DenseMap<int, VGPRSpillToAGPR> VGPRToAGPRSpills;		DenseMap<int, VGPRSpillToAGPR> VGPRToAGPRSpills;

// AGPRs used for VGPR spills.		// AGPRs used for VGPR spills.
SmallVector<MCPhysReg, 32> SpillAGPR;		SmallVector<MCPhysReg, 32> SpillAGPR;

// VGPRs used for AGPR spills.		// VGPRs used for AGPR spills.
SmallVector<MCPhysReg, 32> SpillVGPR;		SmallVector<MCPhysReg, 32> SpillVGPR;

// Emergency stack slot. Sometimes, we create this before finalizing the stack		// Emergency stack slot. Sometimes, we create this before finalizing the stack
// frame, so save it here and add it to the RegScavenger later.		// frame, so save it here and add it to the RegScavenger later.
Optional<int> ScavengeFI;		Optional<int> ScavengeFI;

private:		private:
Register VGPRForAGPRCopy;		Register VGPRForAGPRCopy;

public:		public:
Register getVGPRForAGPRCopy() const {		Register getVGPRForAGPRCopy() const {
return VGPRForAGPRCopy;		return VGPRForAGPRCopy;
}		}

void setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy) {		void setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy) {
VGPRForAGPRCopy = NewVGPRForAGPRCopy;		VGPRForAGPRCopy = NewVGPRForAGPRCopy;
}		}

public: // FIXME
/// If this is set, an SGPR used for save/restore of the register used for the
/// frame pointer.
Register SGPRForFPSaveRestoreCopy;
Optional<int> FramePointerSaveIndex;

/// If this is set, an SGPR used for save/restore of the register used for the
/// base pointer.
Register SGPRForBPSaveRestoreCopy;
Optional<int> BasePointerSaveIndex;

bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg);

public:		public:
SIMachineFunctionInfo(const MachineFunction &MF);		SIMachineFunctionInfo(const MachineFunction &MF);
SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI) = default;		SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI) = default;

MachineFunctionInfo *		MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,		clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
const DenseMap<MachineBasicBlock , MachineBasicBlock > &Src2DstMBB)		const DenseMap<MachineBasicBlock , MachineBasicBlock > &Src2DstMBB)
const override;		const override;
Show All 12 Lines	return (I == SGPRToVGPRSpills.end())
? ArrayRef<SIRegisterInfo::SpilledReg>()		? ArrayRef<SIRegisterInfo::SpilledReg>()
: makeArrayRef(I->second);		: makeArrayRef(I->second);
}		}

ArrayRef<Register> getSGPRSpillVGPRs() const { return SpillVGPRs; }		ArrayRef<Register> getSGPRSpillVGPRs() const { return SpillVGPRs; }
const WWMSpillsMap &getWWMSpills() const { return WWMSpills; }		const WWMSpillsMap &getWWMSpills() const { return WWMSpills; }
const ReservedRegSet &getWWMReservedRegs() const { return WWMReservedRegs; }		const ReservedRegSet &getWWMReservedRegs() const { return WWMReservedRegs; }

		const CustomSGPRSpillsMap &getCustomSGPRSpills() const {
		return CustomSGPRSpills;
		}

		void addToCustomSGPRSpills(Register Reg, CustomSGPRSaveInfo SI) {
		CustomSGPRSpills.insert(std::make_pair(Reg, SI));
		}

		// Check if an entry created for \p Reg in the custom SGPR spills. Return true
		// on success and false otherwise.
		bool hasCustomSGPRSpillEntry(Register Reg) const {
		return CustomSGPRSpills.find(Reg) != CustomSGPRSpills.end();
		}

		// Get the scratch SGPR if allocated to save/restore \p Reg.
		Register getScratchSGPRCopyDstReg(Register Reg) const {
		auto I = CustomSGPRSpills.find(Reg);
		if (I != CustomSGPRSpills.end() &&
		I->second.getKind() == SGPRSaveKind::COPY_TO_SCRATCH_SGPR)
		return I->second.getReg();

		return AMDGPU::NoRegister;
		}

		// Get all scratch SGPRs allocated to copy/restore the custom SGPR spills.
		void getAllScratchSGPRCopyDstRegs(SmallVectorImpl<Register> &Regs) const {
		for (const auto &SI : CustomSGPRSpills) {
		if (SI.second.getKind() == SGPRSaveKind::COPY_TO_SCRATCH_SGPR)
		Regs.push_back(SI.second.getReg());
		}
		}

		// Check if \p FI is allocated for any custom spill to a VGPR lane.
		bool checkIndexInCustomSGPRSpills(int FI) const {
		return find_if(CustomSGPRSpills,
		[FI](const std::pair<Register, CustomSGPRSaveInfo> &SI) {
		return SI.second.getKind() ==
		SGPRSaveKind::SPILL_TO_VGPR_LANE &&
		SI.second.getIndex() == FI;
		}) != CustomSGPRSpills.end();
		}

ArrayRef<SIRegisterInfo::SpilledReg>		ArrayRef<SIRegisterInfo::SpilledReg>
getSGPRToVGPRCustomSpills(int FrameIndex) const {		getSGPRToVGPRCustomSpills(int FrameIndex) const {
auto I = SGPRToVGPRCustomSpills.find(FrameIndex);		auto I = SGPRToVGPRCustomSpills.find(FrameIndex);
return (I == SGPRToVGPRCustomSpills.end())		return (I == SGPRToVGPRCustomSpills.end())
? ArrayRef<SIRegisterInfo::SpilledReg>()		? ArrayRef<SIRegisterInfo::SpilledReg>()
: makeArrayRef(I->second);		: makeArrayRef(I->second);
}		}

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