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Differential D130769 Diff 454777 llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

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llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Linesextern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
initializeGlobalISel(*PR); initializeGlobalISel(*PR);
initializeRISCVMakeCompressibleOptPass(*PR); initializeRISCVMakeCompressibleOptPass(*PR);
initializeRISCVGatherScatterLoweringPass(*PR); initializeRISCVGatherScatterLoweringPass(*PR);
initializeRISCVCodeGenPreparePass(*PR); initializeRISCVCodeGenPreparePass(*PR);
initializeRISCVMergeBaseOffsetOptPass(*PR); initializeRISCVMergeBaseOffsetOptPass(*PR);
initializeRISCVSExtWRemovalPass(*PR); initializeRISCVSExtWRemovalPass(*PR);
initializeRISCVExpandPseudoPass(*PR); initializeRISCVExpandPseudoPass(*PR);
initializeRISCVInsertVSETVLIPass(*PR); initializeRISCVInsertVSETVLIPass(*PR);
initializeRISCVAddSubCombinerPass(*PR);
} }
static StringRef computeDataLayout(const Triple &TT) { static StringRef computeDataLayout(const Triple &TT) {
if (TT.isArch64Bit()) if (TT.isArch64Bit())
return "e-m:e-p:64:64-i64:64-i128:128-n64-S128"; return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported"); assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
return "e-m:e-p:32:32-i64:64-n32-S128"; return "e-m:e-p:32:32-i64:64-n32-S128";
} }
▲ Show 20 Lines • Show All 166 Lines • ▼ Show 20 Lines
bool RISCVPassConfig::addGlobalInstructionSelect() { bool RISCVPassConfig::addGlobalInstructionSelect() {
addPass(new InstructionSelect(getOptLevel())); addPass(new InstructionSelect(getOptLevel()));
return false; return false;
} }
void RISCVPassConfig::addPreSched2() {} void RISCVPassConfig::addPreSched2() {}
void RISCVPassConfig::addPreEmitPass() { void RISCVPassConfig::addPreEmitPass() {
if (TM->getOptLevel() != CodeGenOpt::None)
addPass(createRISCVAddSubCombinerPass());
addPass(&BranchRelaxationPassID); addPass(&BranchRelaxationPassID);
addPass(createRISCVMakeCompressibleOptPass()); addPass(createRISCVMakeCompressibleOptPass());
} }
craig.topperUnsubmitted
Done
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Use != like the other places in this file

craig.topper: Use != like the other places in this file
craig.topperUnsubmitted
Not Done
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Should this be done before branch folding since it removes instructions which could reduce jump distance?

craig.topper: Should this be done before branch folding since it removes instructions which could reduce jump…
eklepilkinaAuthorUnsubmitted
Done
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This impossible, because BranchFolder is set in pipeline before TailDuplicationPass that combines these redundant instructions in one BB.

eklepilkina: This impossible, because `BranchFolder` is set in pipeline before `TailDuplicationPass` that…
craig.topperUnsubmitted
Done
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Sorry. I meant to write BranchRelaxation.

craig.topper: Sorry. I meant to write BranchRelaxation.
void RISCVPassConfig::addPreEmitPass2() { void RISCVPassConfig::addPreEmitPass2() {
addPass(createRISCVExpandPseudoPass()); addPass(createRISCVExpandPseudoPass());
// Schedule the expansion of AMOs at the last possible moment, avoiding the // Schedule the expansion of AMOs at the last possible moment, avoiding the
// possibility for other passes to break the requirements for forward // possibility for other passes to break the requirements for forward
// progress in the LR/SC block. // progress in the LR/SC block.
addPass(createRISCVExpandAtomicPseudoPass()); addPass(createRISCVExpandAtomicPseudoPass());
} }
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