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Differential D132108 Diff 454155 llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

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llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

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} }
def simm16_lsl2_br : Operand<OtherVT> { def simm16_lsl2_br : Operand<OtherVT> {
let ParserMatchClass = SImmAsmOperand<16, "lsl2">; let ParserMatchClass = SImmAsmOperand<16, "lsl2">;
let EncoderMethod = "getImmOpValueAsr2"; let EncoderMethod = "getImmOpValueAsr2";
let DecoderMethod = "decodeSImmOperand<16, 2>"; let DecoderMethod = "decodeSImmOperand<16, 2>";
} }
def simm20 : Operand<GRLenVT> { class SImm20Operand : Operand<GRLenVT> {
let ParserMatchClass = SImmAsmOperand<20>;
let DecoderMethod = "decodeSImmOperand<20>"; let DecoderMethod = "decodeSImmOperand<20>";
} }
def simm20 : SImm20Operand {
let ParserMatchClass = SImmAsmOperand<20>;
}
def simm20_pcalau12i : SImm20Operand {
let ParserMatchClass = SImmAsmOperand<20, "pcalau12i">;
}
def simm21_lsl2 : Operand<OtherVT> { def simm21_lsl2 : Operand<OtherVT> {
let ParserMatchClass = SImmAsmOperand<21, "lsl2">; let ParserMatchClass = SImmAsmOperand<21, "lsl2">;
let EncoderMethod = "getImmOpValueAsr2"; let EncoderMethod = "getImmOpValueAsr2";
let DecoderMethod = "decodeSImmOperand<21, 2>"; let DecoderMethod = "decodeSImmOperand<21, 2>";
} }
def simm26_lsl2 : Operand<OtherVT> { // TODO: Need split the ParserMethod/PredicateMethod for call/jump/tailcall.
let ParserMatchClass = SImmAsmOperand<26, "lsl2">; def SImm26Operand: AsmOperandClass {
let Name = "SImm26Operand";
let RenderMethod = "addImmOperands";
let DiagnosticType = "InvalidSImm26Operand";
let ParserMethod = "parseSImm26Operand";
}
// A symbol or an imm used in B/PseudoBR.
def simm26_b : Operand<OtherVT> {
let ParserMatchClass = SImm26Operand;
let EncoderMethod = "getImmOpValueAsr2";
let DecoderMethod = "decodeSImmOperand<26, 2>";
}
// A symbol or an imm used in BL/PseudoCALL.
def simm26_bl : Operand<GRLenVT> {
let ParserMatchClass = SImm26Operand;
let EncoderMethod = "getImmOpValueAsr2"; let EncoderMethod = "getImmOpValueAsr2";
let DecoderMethod = "decodeSImmOperand<26, 2>"; let DecoderMethod = "decodeSImmOperand<26, 2>";
} }
// Standalone (codegen-only) immleaf patterns. // Standalone (codegen-only) immleaf patterns.
// A 12-bit signed immediate plus one where the imm range will be [-2047, 2048]. // A 12-bit signed immediate plus one where the imm range will be [-2047, 2048].
def simm12_plus1 : ImmLeaf<GRLenVT, def simm12_plus1 : ImmLeaf<GRLenVT,
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def fpimm1 : PatLeaf<(fpimm), [{return N->isExactlyValue(+1.0);}]>; def fpimm1 : PatLeaf<(fpimm), [{return N->isExactlyValue(+1.0);}]>;
// Return an immediate subtracted from 32. // Return an immediate subtracted from 32.
def ImmSubFrom32 : SDNodeXForm<imm, [{ def ImmSubFrom32 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(32 - N->getZExtValue(), SDLoc(N), return CurDAG->getTargetConstant(32 - N->getZExtValue(), SDLoc(N),
N->getValueType(0)); N->getValueType(0));
}]>; }]>;
def CallSymbol: AsmOperandClass {
let Name = "CallSymbol";
let RenderMethod = "addImmOperands";
let PredicateMethod = "isImm";
}
// A bare symbol used in call only.
def call_symbol : Operand<iPTR> {
let ParserMatchClass = CallSymbol;
}
def BaseAddr : ComplexPattern<iPTR, 1, "SelectBaseAddr">; def BaseAddr : ComplexPattern<iPTR, 1, "SelectBaseAddr">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instruction Formats // Instruction Formats
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
include "LoongArchInstrFormats.td" include "LoongArchInstrFormats.td"
include "LoongArchFloatInstrFormats.td" include "LoongArchFloatInstrFormats.td"
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} }
class BrCCZ_1RI21<bits<6> op, string opstr> class BrCCZ_1RI21<bits<6> op, string opstr>
: Fmt1RI21<op, (outs), (ins GPR:$rj, simm21_lsl2:$imm21), opstr, : Fmt1RI21<op, (outs), (ins GPR:$rj, simm21_lsl2:$imm21), opstr,
"$rj, $imm21"> { "$rj, $imm21"> {
let isBranch = 1; let isBranch = 1;
let isTerminator = 1; let isTerminator = 1;
} }
class Br_I26<bits<6> op, string opstr> class Br_I26<bits<6> op, string opstr>
: FmtI26<op, (outs), (ins simm26_lsl2:$imm26), opstr, "$imm26"> { : FmtI26<op, (outs), (ins simm26_b:$imm26), opstr, "$imm26"> {
let isBranch = 1; let isBranch = 1;
let isTerminator = 1; let isTerminator = 1;
} }
let mayLoad = 1 in { let mayLoad = 1 in {
class LOAD_3R<bits<17> op, string opstr> class LOAD_3R<bits<17> op, string opstr>
: Fmt3R<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk), opstr, "$rd, $rj, $rk">; : Fmt3R<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk), opstr, "$rd, $rj, $rk">;
class LOAD_2RI12<bits<10> op, string opstr> class LOAD_2RI12<bits<10> op, string opstr>
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def ALSL_W : ALU_3RI2<0b000000000000010, "alsl.w", uimm2_plus1>; def ALSL_W : ALU_3RI2<0b000000000000010, "alsl.w", uimm2_plus1>;
def LU12I_W : ALU_1RI20<0b0001010, "lu12i.w", simm20>; def LU12I_W : ALU_1RI20<0b0001010, "lu12i.w", simm20>;
def SLT : ALU_3R<0b00000000000100100, "slt">; def SLT : ALU_3R<0b00000000000100100, "slt">;
def SLTU : ALU_3R<0b00000000000100101, "sltu">; def SLTU : ALU_3R<0b00000000000100101, "sltu">;
def SLTI : ALU_2RI12<0b0000001000, "slti", simm12>; def SLTI : ALU_2RI12<0b0000001000, "slti", simm12>;
def SLTUI : ALU_2RI12<0b0000001001, "sltui", simm12>; def SLTUI : ALU_2RI12<0b0000001001, "sltui", simm12>;
def PCADDI : ALU_1RI20<0b0001100, "pcaddi", simm20>; def PCADDI : ALU_1RI20<0b0001100, "pcaddi", simm20>;
def PCADDU12I : ALU_1RI20<0b0001110, "pcaddu12i", simm20>; def PCADDU12I : ALU_1RI20<0b0001110, "pcaddu12i", simm20>;
def PCALAU12I : ALU_1RI20<0b0001101, "pcalau12i", simm20>; def PCALAU12I : ALU_1RI20<0b0001101, "pcalau12i", simm20_pcalau12i>;
def AND : ALU_3R<0b00000000000101001, "and">; def AND : ALU_3R<0b00000000000101001, "and">;
def OR : ALU_3R<0b00000000000101010, "or">; def OR : ALU_3R<0b00000000000101010, "or">;
def NOR : ALU_3R<0b00000000000101000, "nor">; def NOR : ALU_3R<0b00000000000101000, "nor">;
def XOR : ALU_3R<0b00000000000101011, "xor">; def XOR : ALU_3R<0b00000000000101011, "xor">;
def ANDN : ALU_3R<0b00000000000101101, "andn">; def ANDN : ALU_3R<0b00000000000101101, "andn">;
def ORN : ALU_3R<0b00000000000101100, "orn">; def ORN : ALU_3R<0b00000000000101100, "orn">;
def ANDI : ALU_2RI12<0b0000001101, "andi", uimm12>; def ANDI : ALU_2RI12<0b0000001101, "andi", uimm12>;
def ORI : ALU_2RI12<0b0000001110, "ori", uimm12>; def ORI : ALU_2RI12<0b0000001110, "ori", uimm12>;
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def BLT : BrCC_2RI16<0b011000, "blt">; def BLT : BrCC_2RI16<0b011000, "blt">;
def BGE : BrCC_2RI16<0b011001, "bge">; def BGE : BrCC_2RI16<0b011001, "bge">;
def BLTU : BrCC_2RI16<0b011010, "bltu">; def BLTU : BrCC_2RI16<0b011010, "bltu">;
def BGEU : BrCC_2RI16<0b011011, "bgeu">; def BGEU : BrCC_2RI16<0b011011, "bgeu">;
def BEQZ : BrCCZ_1RI21<0b010000, "beqz">; def BEQZ : BrCCZ_1RI21<0b010000, "beqz">;
def BNEZ : BrCCZ_1RI21<0b010001, "bnez">; def BNEZ : BrCCZ_1RI21<0b010001, "bnez">;
def B : Br_I26<0b010100, "b">; def B : Br_I26<0b010100, "b">;
let isCall = 1 in let isCall = 1, Defs=[R1] in
def BL : FmtI26<0b010101, (outs), (ins simm26_lsl2:$imm26), "bl", "$imm26">; def BL : FmtI26<0b010101, (outs), (ins simm26_bl:$imm26), "bl", "$imm26">;
def JIRL : Fmt2RI16<0b010011, (outs GPR:$rd), def JIRL : Fmt2RI16<0b010011, (outs GPR:$rd),
(ins GPR:$rj, simm16_lsl2:$imm16), "jirl", (ins GPR:$rj, simm16_lsl2:$imm16), "jirl",
"$rd, $rj, $imm16">; "$rd, $rj, $imm16">;
// Common Memory Access Instructions // Common Memory Access Instructions
def LD_B : LOAD_2RI12<0b0010100000, "ld.b">; def LD_B : LOAD_2RI12<0b0010100000, "ld.b">;
def LD_H : LOAD_2RI12<0b0010100001, "ld.h">; def LD_H : LOAD_2RI12<0b0010100001, "ld.h">;
def LD_W : LOAD_2RI12<0b0010100010, "ld.w">; def LD_W : LOAD_2RI12<0b0010100010, "ld.w">;
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def : Pat<(brcond GPR:$rj, bb:$imm21), (BNEZ GPR:$rj, bb:$imm21)>; def : Pat<(brcond GPR:$rj, bb:$imm21), (BNEZ GPR:$rj, bb:$imm21)>;
def : Pat<(brcond (GRLenVT (seteq GPR:$rj, 0)), bb:$imm21), def : Pat<(brcond (GRLenVT (seteq GPR:$rj, 0)), bb:$imm21),
(BEQZ GPR:$rj, bb:$imm21)>; (BEQZ GPR:$rj, bb:$imm21)>;
def : Pat<(brcond (GRLenVT (setne GPR:$rj, 0)), bb:$imm21), def : Pat<(brcond (GRLenVT (setne GPR:$rj, 0)), bb:$imm21),
(BNEZ GPR:$rj, bb:$imm21)>; (BNEZ GPR:$rj, bb:$imm21)>;
let isBarrier = 1, isBranch = 1, isTerminator = 1 in let isBarrier = 1, isBranch = 1, isTerminator = 1 in
def PseudoBR : Pseudo<(outs), (ins simm26_lsl2:$imm26), [(br bb:$imm26)]>, def PseudoBR : Pseudo<(outs), (ins simm26_b:$imm26), [(br bb:$imm26)]>,
PseudoInstExpansion<(B simm26_lsl2:$imm26)>; PseudoInstExpansion<(B simm26_b:$imm26)>;
let isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in let isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in
def PseudoBRIND : Pseudo<(outs), (ins GPR:$rj, simm16_lsl2:$imm16), []>, def PseudoBRIND : Pseudo<(outs), (ins GPR:$rj, simm16_lsl2:$imm16), []>,
PseudoInstExpansion<(JIRL R0, GPR:$rj, simm16_lsl2:$imm16)>; PseudoInstExpansion<(JIRL R0, GPR:$rj, simm16_lsl2:$imm16)>;
def : Pat<(brind GPR:$rj), (PseudoBRIND GPR:$rj, 0)>; def : Pat<(brind GPR:$rj), (PseudoBRIND GPR:$rj, 0)>;
def : Pat<(brind (add GPR:$rj, simm16_lsl2:$imm16)), def : Pat<(brind (add GPR:$rj, simm16_lsl2:$imm16)),
(PseudoBRIND GPR:$rj, simm16_lsl2:$imm16)>; (PseudoBRIND GPR:$rj, simm16_lsl2:$imm16)>;
let isCall = 1, Defs = [R1] in let isCall = 1, Defs = [R1] in
def PseudoCALL : Pseudo<(outs), (ins call_symbol:$func), []> { def PseudoCALL : Pseudo<(outs), (ins simm26_bl:$func), []> {
let AsmString = "bl\t$func"; let AsmString = "bl\t$func";
} }
def : Pat<(loongarch_call tglobaladdr:$func), (PseudoCALL tglobaladdr:$func)>; def : Pat<(loongarch_call tglobaladdr:$func), (PseudoCALL tglobaladdr:$func)>;
def : Pat<(loongarch_call texternalsym:$func), (PseudoCALL texternalsym:$func)>; def : Pat<(loongarch_call texternalsym:$func), (PseudoCALL texternalsym:$func)>;
let isCall = 1, Defs = [R1] in let isCall = 1, Defs = [R1] in
def PseudoCALLIndirect : Pseudo<(outs), (ins GPR:$rj), def PseudoCALLIndirect : Pseudo<(outs), (ins GPR:$rj),
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