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llvm/lib/Target/RISCV/RISCVRegisterInfo.td
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| // Integer registers | // Integer registers | ||||
| // CostPerUse is set higher for registers that may not be compressible as they | // CostPerUse is set higher for registers that may not be compressible as they | ||||
| // are not part of GPRC, the most restrictive register class used by the | // are not part of GPRC, the most restrictive register class used by the | ||||
| // compressed instruction set. This will influence the greedy register | // compressed instruction set. This will influence the greedy register | ||||
| // allocator to reduce the use of registers that can't be encoded in 16 bit | // allocator to reduce the use of registers that can't be encoded in 16 bit | ||||
| // instructions. | // instructions. | ||||
| let RegAltNameIndices = [ABIRegAltName] in { | let RegAltNameIndices = [ABIRegAltName] in { | ||||
| let isConstant = true in | |||||
| def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>; | def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>; | ||||
| let CostPerUse = [0, 1] in { | let CostPerUse = [0, 1] in { | ||||
| def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>; | def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>; | ||||
| def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>; | def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>; | ||||
| def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>; | def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>; | ||||
| def X4 : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>; | def X4 : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>; | ||||
| def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>; | def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>; | ||||
| def X6 : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>; | def X6 : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>; | ||||
| ▲ Show 20 Lines • Show All 365 Lines • ▼ Show 20 Lines | def V#Index#M8 : RISCVRegWithSubRegs<Index, "v"#Index, | ||||
| let SubRegIndices = [sub_vrm4_0, sub_vrm4_1]; | let SubRegIndices = [sub_vrm4_0, sub_vrm4_1]; | ||||
| } | } | ||||
| } | } | ||||
| def VTYPE : RISCVReg<0, "vtype", ["vtype"]>; | def VTYPE : RISCVReg<0, "vtype", ["vtype"]>; | ||||
| def VL : RISCVReg<0, "vl", ["vl"]>; | def VL : RISCVReg<0, "vl", ["vl"]>; | ||||
| def VXSAT : RISCVReg<0, "vxsat", ["vxsat"]>; | def VXSAT : RISCVReg<0, "vxsat", ["vxsat"]>; | ||||
| def VXRM : RISCVReg<0, "vxrm", ["vxrm"]>; | def VXRM : RISCVReg<0, "vxrm", ["vxrm"]>; | ||||
| let isConstant = true in | |||||
| def VLENB : RISCVReg<0, "vlenb", ["vlenb"]>, | def VLENB : RISCVReg<0, "vlenb", ["vlenb"]>, | ||||
| DwarfRegNum<[!add(4096, SysRegVLENB.Encoding)]>; | DwarfRegNum<[!add(4096, SysRegVLENB.Encoding)]>; | ||||
| } | } | ||||
| def VCSR : RegisterClass<"RISCV", [XLenVT], 32, | def VCSR : RegisterClass<"RISCV", [XLenVT], 32, | ||||
| (add VTYPE, VL, VLENB)> { | (add VTYPE, VL, VLENB)> { | ||||
| let RegInfos = XLenRI; | let RegInfos = XLenRI; | ||||
| } | } | ||||
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