Differential D131962 Diff 452995 llvm/lib/Target/AMDGPU/SIRegisterInfo.td

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llvm/lib/Target/AMDGPU/SIRegisterInfo.td

Show First 20 Lines • Show All 137 Lines • ▼ Show 20 Lines	class SIRegisterClass <string n, list<ValueType> rTypes, int Align, dag rList>

// These need to be kept in sync with the enum SIRCFlags.		// These need to be kept in sync with the enum SIRCFlags.
let TSFlags{0} = HasVGPR;		let TSFlags{0} = HasVGPR;
let TSFlags{1} = HasAGPR;		let TSFlags{1} = HasAGPR;
let TSFlags{2} = HasSGPR;		let TSFlags{2} = HasSGPR;
}		}

multiclass SIRegLoHi16 <string n, bits<16> regIdx, bit ArtificialHigh = 1,		multiclass SIRegLoHi16 <string n, bits<16> regIdx, bit ArtificialHigh = 1,
bit HWEncodingHigh = 0> {		bit HWEncodingHigh = 0> {
		jrtc27Unsubmitted Not Done Reply Inline Actions Not used any more jrtc27: Not used any more
// There is no special encoding for 16 bit subregs, these are not real		// There is no special encoding for 16 bit subregs, these are not real
// registers but rather operands for instructions preserving other 16 bits		// registers but rather operands for instructions preserving other 16 bits
// of the result or reading just 16 bits of a 32 bit VGPR.		// of the result or reading just 16 bits of a 32 bit VGPR.
// It is encoded as a corresponding 32 bit register.		// It is encoded as a corresponding 32 bit register.
// Non-VGPR register classes use it as we need to have matching subregisters		// Non-VGPR register classes use it as we need to have matching subregisters
// to move instructions and data between ALUs.		// to move instructions and data between ALUs.
def _LO16 : SIReg<n#".l", regIdx> {		def _LO16 : SIReg<n#".l", regIdx> {
let HWEncoding{8} = HWEncodingHigh;		let HWEncoding{8} = HWEncodingHigh;
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// Encoding changes between subtarget generations.		// Encoding changes between subtarget generations.
// See also Utils/AMDGPUBaseInfo.cpp MAP_REG2REG.		// See also Utils/AMDGPUBaseInfo.cpp MAP_REG2REG.
defm M0_gfxpre11 : SIRegLoHi16 <"m0", 124>;		defm M0_gfxpre11 : SIRegLoHi16 <"m0", 124>;
defm M0_gfx11plus : SIRegLoHi16 <"m0", 125>;		defm M0_gfx11plus : SIRegLoHi16 <"m0", 125>;
defm M0 : SIRegLoHi16 <"m0", 0>;		defm M0 : SIRegLoHi16 <"m0", 0>;

defm SGPR_NULL_gfxpre11 : SIRegLoHi16 <"null", 125>;		defm SGPR_NULL_gfxpre11 : SIRegLoHi16 <"null", 125>;
defm SGPR_NULL_gfx11plus : SIRegLoHi16 <"null", 124>;		defm SGPR_NULL_gfx11plus : SIRegLoHi16 <"null", 124>;
		let isConstant = true in {
defm SGPR_NULL : SIRegLoHi16 <"null", 0>;		defm SGPR_NULL : SIRegLoHi16 <"null", 0>;
defm SGPR_NULL_HI : SIRegLoHi16 <"", 0>;		defm SGPR_NULL_HI : SIRegLoHi16 <"", 0>;
		} // isConstant = true
		jrtc27Unsubmitted Done Reply Inline Actions This wasn't constant before jrtc27: This wasn't constant before
		arichardsonAuthorUnsubmitted Done Reply Inline Actions That's true, but since it's a subreg if SGPR_NULL64 I assumed it must be. arichardson: That's true, but since it's a subreg if SGPR_NULL64 I assumed it must be.

def SGPR_NULL64 :		def SGPR_NULL64 :
RegisterWithSubRegs<"null", [SGPR_NULL, SGPR_NULL_HI]> {		RegisterWithSubRegs<"null", [SGPR_NULL, SGPR_NULL_HI]> {
let Namespace = "AMDGPU";		let Namespace = "AMDGPU";
let SubRegIndices = [sub0, sub1];		let SubRegIndices = [sub0, sub1];
let HWEncoding = SGPR_NULL.HWEncoding;		let HWEncoding = SGPR_NULL.HWEncoding;
		let isConstant = true;
}		}
		let isConstant = true in {
foadUnsubmitted Not Done Reply Inline Actions Please don't remove the blank line :) foad: Please don't remove the blank line :)
defm SRC_SHARED_BASE : SIRegLoHi16<"src_shared_base", 235>;		defm SRC_SHARED_BASE : SIRegLoHi16<"src_shared_base", 235>;
defm SRC_SHARED_LIMIT : SIRegLoHi16<"src_shared_limit", 236>;		defm SRC_SHARED_LIMIT : SIRegLoHi16<"src_shared_limit", 236>;
defm SRC_PRIVATE_BASE : SIRegLoHi16<"src_private_base", 237>;		defm SRC_PRIVATE_BASE : SIRegLoHi16<"src_private_base", 237>;
defm SRC_PRIVATE_LIMIT : SIRegLoHi16<"src_private_limit", 238>;		defm SRC_PRIVATE_LIMIT : SIRegLoHi16<"src_private_limit", 238>;
defm SRC_POPS_EXITING_WAVE_ID : SIRegLoHi16<"src_pops_exiting_wave_id", 239>;		defm SRC_POPS_EXITING_WAVE_ID : SIRegLoHi16<"src_pops_exiting_wave_id", 239>;
		} // isConstant = true
		jrtc27Unsubmitted Done Reply Inline Actions This wasn't constant before jrtc27: This wasn't constant before
		arichardsonAuthorUnsubmitted Done Reply Inline Actions fixed. arichardson: fixed.

// Not addressable		// Not addressable
def MODE : SIReg <"mode", 0>;		def MODE : SIReg <"mode", 0>;

def LDS_DIRECT : SIReg <"src_lds_direct", 254> {		def LDS_DIRECT : SIReg <"src_lds_direct", 254> {
// There is no physical register corresponding to this. This is an		// There is no physical register corresponding to this. This is an
// encoding value in a source field, which will ultimately trigger a		// encoding value in a source field, which will ultimately trigger a
// read from m0.		// read from m0.
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