Changeset View
Changeset View
Standalone View
Standalone View
llvm/lib/Target/AMDGPU/SIRegisterInfo.h
| Show First 20 Lines • Show All 283 Lines • ▼ Show 20 Lines | public: | ||||
| const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI, | const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI, | ||||
| Register Reg) const; | Register Reg) const; | ||||
| bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const; | bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const; | ||||
| bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const; | bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const; | ||||
| bool isVectorRegister(const MachineRegisterInfo &MRI, Register Reg) const { | bool isVectorRegister(const MachineRegisterInfo &MRI, Register Reg) const { | ||||
| return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); | return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); | ||||
| } | } | ||||
| bool isConstantPhysReg(MCRegister PhysReg) const override; | |||||
| bool isDivergentRegClass(const TargetRegisterClass *RC) const override { | bool isDivergentRegClass(const TargetRegisterClass *RC) const override { | ||||
| return !isSGPRClass(RC); | return !isSGPRClass(RC); | ||||
| } | } | ||||
| ArrayRef<int16_t> getRegSplitParts(const TargetRegisterClass *RC, | ArrayRef<int16_t> getRegSplitParts(const TargetRegisterClass *RC, | ||||
| unsigned EltSize) const; | unsigned EltSize) const; | ||||
| bool shouldCoalesce(MachineInstr *MI, | bool shouldCoalesce(MachineInstr *MI, | ||||
| ▲ Show 20 Lines • Show All 122 Lines • Show Last 20 Lines | |||||