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Differential D131962 Diff 452982 llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

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llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Show First 20 Lines • Show All 3,077 Lines • ▼ Show 20 LinesSIRegisterInfo::getProperlyAlignedRC(const TargetRegisterClass *RC) const {
if (isAGPRClass(RC)) if (isAGPRClass(RC))
return getAlignedAGPRClassForBitWidth(Size); return getAlignedAGPRClassForBitWidth(Size);
if (isVectorSuperClass(RC)) if (isVectorSuperClass(RC))
return getAlignedVectorSuperClassForBitWidth(Size); return getAlignedVectorSuperClassForBitWidth(Size);
return RC; return RC;
} }
bool SIRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
switch (PhysReg) {
case AMDGPU::SGPR_NULL:
case AMDGPU::SGPR_NULL64:
case AMDGPU::SGPR_NULL_HI:
case AMDGPU::SRC_SHARED_BASE:
case AMDGPU::SRC_PRIVATE_BASE:
case AMDGPU::SRC_SHARED_LIMIT:
case AMDGPU::SRC_PRIVATE_LIMIT:
return true;
default:
return false;
}
}
ArrayRef<MCPhysReg> ArrayRef<MCPhysReg>
SIRegisterInfo::getAllSGPR128(const MachineFunction &MF) const { SIRegisterInfo::getAllSGPR128(const MachineFunction &MF) const {
return makeArrayRef(AMDGPU::SGPR_128RegClass.begin(), return makeArrayRef(AMDGPU::SGPR_128RegClass.begin(),
ST.getMaxNumSGPRs(MF) / 4); ST.getMaxNumSGPRs(MF) / 4);
} }
ArrayRef<MCPhysReg> ArrayRef<MCPhysReg>
SIRegisterInfo::getAllSGPR64(const MachineFunction &MF) const { SIRegisterInfo::getAllSGPR64(const MachineFunction &MF) const {
return makeArrayRef(AMDGPU::SGPR_64RegClass.begin(), return makeArrayRef(AMDGPU::SGPR_64RegClass.begin(),
ST.getMaxNumSGPRs(MF) / 2); ST.getMaxNumSGPRs(MF) / 2);
} }
ArrayRef<MCPhysReg> ArrayRef<MCPhysReg>
SIRegisterInfo::getAllSGPR32(const MachineFunction &MF) const { SIRegisterInfo::getAllSGPR32(const MachineFunction &MF) const {
return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(), ST.getMaxNumSGPRs(MF)); return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(), ST.getMaxNumSGPRs(MF));
} }