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Differential D131958 Diff 452969 llvm/test/CodeGen/RISCV/double-convert.ll

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llvm/test/CodeGen/RISCV/double-convert.ll

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; RV32I-NEXT: lui a0, 278016 ; RV32I-NEXT: lui a0, 278016
; RV32I-NEXT: addi s3, a0, -1 ; RV32I-NEXT: addi s3, a0, -1
; RV32I-NEXT: li a2, -1 ; RV32I-NEXT: li a2, -1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a3, s3 ; RV32I-NEXT: mv a3, s3
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: lui a3, 802304 ; RV32I-NEXT: lui a3, 802304
; RV32I-NEXT: li s2, 0 ; RV32I-NEXT: li s2, 0
arichardsonAuthorUnsubmitted
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Still got a load of zero into a saved register here, not quite sure why. blt s2, s4, .LBB12_4 should be able to use the zero register.

arichardson: Still got a load of zero into a saved register here, not quite sure why. `blt s2, s4, .LBB12_4`…
asbUnsubmitted
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Yes, there's something weird going on in general with selection of the zero register. See D130809 and the bug tracking this issue. I'm not sure if it's a general problem with register coalescer or if there's some hook that's not set properly somewhere.

asb: Yes, there's something weird going on in general with selection of the zero register. See…
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s6, a0 ; RV32I-NEXT: mv s6, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __fixdfdi@plt ; RV32I-NEXT: call __fixdfdi@plt
; RV32I-NEXT: mv s5, a1 ; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: bltz s6, .LBB12_2 ; RV32I-NEXT: bltz s6, .LBB12_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: .LBB12_2: # %start ; RV32I-NEXT: .LBB12_2: # %start
; RV32I-NEXT: li s6, -1 ; RV32I-NEXT: li s6, -1
; RV32I-NEXT: blt s2, s4, .LBB12_4 ; RV32I-NEXT: blt s2, s4, .LBB12_4
; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv s6, a1 ; RV32I-NEXT: mv s6, a1
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; RV32I-NEXT: li s0, 0 ; RV32I-NEXT: li s0, 0
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lui a3, 790016 ; RV32I-NEXT: lui a3, 790016
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __fixdfsi@plt ; RV32I-NEXT: call __fixdfsi@plt
; RV32I-NEXT: lui s5, 1048568 ; RV32I-NEXT: lui s5, 1048568
; RV32I-NEXT: bltz s4, .LBB26_2 ; RV32I-NEXT: bltz s4, .LBB26_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
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; RV32I-NEXT: lui a3, 263676 ; RV32I-NEXT: lui a3, 263676
; RV32I-NEXT: li s0, 0 ; RV32I-NEXT: li s0, 0
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lui a3, 787968 ; RV32I-NEXT: lui a3, 787968
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __fixdfsi@plt ; RV32I-NEXT: call __fixdfsi@plt
; RV32I-NEXT: li a1, -128 ; RV32I-NEXT: li a1, -128
; RV32I-NEXT: bltz s4, .LBB30_2 ; RV32I-NEXT: bltz s4, .LBB30_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
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