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llvm/lib/Target/VE/VERegisterInfo.td
| Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Lines | |||||
| // Vector registers - 64 bits wide 256 elements | // Vector registers - 64 bits wide 256 elements | ||||
| foreach I = 0-63 in | foreach I = 0-63 in | ||||
| def V#I : VEVecReg<I, "v"#I, [], ["v"#I]>, DwarfRegNum<[!add(64,I)]>; | def V#I : VEVecReg<I, "v"#I, [], ["v"#I]>, DwarfRegNum<[!add(64,I)]>; | ||||
| // Vector Index Register | // Vector Index Register | ||||
| def VIX : VEVecReg<255, "vix", [], ["vix"]>; | def VIX : VEVecReg<255, "vix", [], ["vix"]>; | ||||
| // Vector mask registers - 256 bits wide | // Vector mask registers - 256 bits wide | ||||
| foreach I = 0-15 in | def VM0 : VEMaskReg<0, "vm0", [], ["vm0"]>, DwarfRegNum<[128]> { let isConstant = true; } | ||||
| foreach I = 1-15 in | |||||
| def VM#I : VEMaskReg<I, "vm"#I, [], ["vm"#I]>, DwarfRegNum<[!add(128,I)]>; | def VM#I : VEMaskReg<I, "vm"#I, [], ["vm"#I]>, DwarfRegNum<[!add(128,I)]>; | ||||
| // Aliases of VMs to use as a pair of two VM for packed instructions | // Aliases of VMs to use as a pair of two VM for packed instructions | ||||
| def VMP0 : VEMaskReg<0, "vm0", [], ["vm0"]>; | def VMP0 : VEMaskReg<0, "vm0", [], ["vm0"]> { let isConstant = true; } | ||||
| let SubRegIndices = [sub_vm_even, sub_vm_odd], CoveredBySubRegs = 1 in | let SubRegIndices = [sub_vm_even, sub_vm_odd], CoveredBySubRegs = 1 in | ||||
| foreach I = 1-7 in | foreach I = 1-7 in | ||||
| def VMP#I : VEMaskReg<!shl(I,1), "vmp"#I, | def VMP#I : VEMaskReg<!shl(I,1), "vmp"#I, | ||||
| [!cast<VEMaskReg>("VM"#!shl(I,1)), | [!cast<VEMaskReg>("VM"#!shl(I,1)), | ||||
| !cast<VEMaskReg>("VM"#!add(!shl(I,1),1))], | !cast<VEMaskReg>("VM"#!add(!shl(I,1),1))], | ||||
| ["vm"#!shl(I,1)]>; | ["vm"#!shl(I,1)]>; | ||||
| Show All 33 Lines | |||||