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llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
| Show All 34 Lines | |||||
| let FallbackRegAltNameIndex = NoRegAltName in | let FallbackRegAltNameIndex = NoRegAltName in | ||||
| def RegAliasName : RegAltNameIndex; | def RegAliasName : RegAltNameIndex; | ||||
| } // Namespace = "LoongArch" | } // Namespace = "LoongArch" | ||||
| // Integer registers | // Integer registers | ||||
| let RegAltNameIndices = [RegAliasName] in { | let RegAltNameIndices = [RegAliasName] in { | ||||
| def R0 : LoongArchReg<0, "r0", ["zero"]>, DwarfRegNum<[0]>; | def R0 : LoongArchReg<0, "r0", ["zero"]>, DwarfRegNum<[0]> { let isConstant = true; } | ||||
| def R1 : LoongArchReg<1, "r1", ["ra"]>, DwarfRegNum<[1]>; | def R1 : LoongArchReg<1, "r1", ["ra"]>, DwarfRegNum<[1]>; | ||||
| def R2 : LoongArchReg<2, "r2", ["tp"]>, DwarfRegNum<[2]>; | def R2 : LoongArchReg<2, "r2", ["tp"]>, DwarfRegNum<[2]>; | ||||
| def R3 : LoongArchReg<3, "r3", ["sp"]>, DwarfRegNum<[3]>; | def R3 : LoongArchReg<3, "r3", ["sp"]>, DwarfRegNum<[3]>; | ||||
| def R4 : LoongArchReg<4, "r4", ["a0"]>, DwarfRegNum<[4]>; | def R4 : LoongArchReg<4, "r4", ["a0"]>, DwarfRegNum<[4]>; | ||||
| def R5 : LoongArchReg<5, "r5", ["a1"]>, DwarfRegNum<[5]>; | def R5 : LoongArchReg<5, "r5", ["a1"]>, DwarfRegNum<[5]>; | ||||
| def R6 : LoongArchReg<6, "r6", ["a2"]>, DwarfRegNum<[6]>; | def R6 : LoongArchReg<6, "r6", ["a2"]>, DwarfRegNum<[6]>; | ||||
| def R7 : LoongArchReg<7, "r7", ["a3"]>, DwarfRegNum<[7]>; | def R7 : LoongArchReg<7, "r7", ["a3"]>, DwarfRegNum<[7]>; | ||||
| def R8 : LoongArchReg<8, "r8", ["a4"]>, DwarfRegNum<[8]>; | def R8 : LoongArchReg<8, "r8", ["a4"]>, DwarfRegNum<[8]>; | ||||
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