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Differential D131958 Diff 452969 llvm/lib/Target/AMDGPU/SIRegisterInfo.td

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llvm/lib/Target/AMDGPU/SIRegisterInfo.td

Show First 20 Lines • Show All 137 Lines • ▼ Show 20 Linesclass SIRegisterClass <string n, list<ValueType> rTypes, int Align, dag rList>
// These need to be kept in sync with the enum SIRCFlags. // These need to be kept in sync with the enum SIRCFlags.
let TSFlags{0} = HasVGPR; let TSFlags{0} = HasVGPR;
let TSFlags{1} = HasAGPR; let TSFlags{1} = HasAGPR;
let TSFlags{2} = HasSGPR; let TSFlags{2} = HasSGPR;
} }
multiclass SIRegLoHi16 <string n, bits<16> regIdx, bit ArtificialHigh = 1, multiclass SIRegLoHi16 <string n, bits<16> regIdx, bit ArtificialHigh = 1,
bit HWEncodingHigh = 0> { bit HWEncodingHigh = 0, bit Constant = false> {
// There is no special encoding for 16 bit subregs, these are not real // There is no special encoding for 16 bit subregs, these are not real
// registers but rather operands for instructions preserving other 16 bits // registers but rather operands for instructions preserving other 16 bits
// of the result or reading just 16 bits of a 32 bit VGPR. // of the result or reading just 16 bits of a 32 bit VGPR.
// It is encoded as a corresponding 32 bit register. // It is encoded as a corresponding 32 bit register.
// Non-VGPR register classes use it as we need to have matching subregisters // Non-VGPR register classes use it as we need to have matching subregisters
// to move instructions and data between ALUs. // to move instructions and data between ALUs.
def _LO16 : SIReg<n#".l", regIdx> { def _LO16 : SIReg<n#".l", regIdx> {
let HWEncoding{8} = HWEncodingHigh; let HWEncoding{8} = HWEncodingHigh;
let isConstant = Constant;
} }
def _HI16 : SIReg<!if(ArtificialHigh, "", n#".h"), regIdx> { def _HI16 : SIReg<!if(ArtificialHigh, "", n#".h"), regIdx> {
let isArtificial = ArtificialHigh; let isArtificial = ArtificialHigh;
let HWEncoding{8} = HWEncodingHigh; let HWEncoding{8} = HWEncodingHigh;
let isConstant = Constant;
} }
def "" : RegisterWithSubRegs<n, [!cast<Register>(NAME#"_LO16"), def "" : RegisterWithSubRegs<n, [!cast<Register>(NAME#"_LO16"),
!cast<Register>(NAME#"_HI16")]> { !cast<Register>(NAME#"_HI16")]> {
let Namespace = "AMDGPU"; let Namespace = "AMDGPU";
let SubRegIndices = [lo16, hi16]; let SubRegIndices = [lo16, hi16];
let CoveredBySubRegs = !not(ArtificialHigh); let CoveredBySubRegs = !not(ArtificialHigh);
let HWEncoding = regIdx; let HWEncoding = regIdx;
let HWEncoding{8} = HWEncodingHigh; let HWEncoding{8} = HWEncodingHigh;
let isConstant = Constant;
} }
} }
multiclass SIRegLoHi16Const<string n, bits<16> regIdx, bit ArtificialHigh = 1,
bit HWEncodingHigh = 0>
: SIRegLoHi16<n, regIdx, ArtificialHigh, HWEncodingHigh, true>;
// Special Registers // Special Registers
defm VCC_LO : SIRegLoHi16<"vcc_lo", 106>; defm VCC_LO : SIRegLoHi16<"vcc_lo", 106>;
defm VCC_HI : SIRegLoHi16<"vcc_hi", 107>; defm VCC_HI : SIRegLoHi16<"vcc_hi", 107>;
// Pseudo-registers: Used as placeholders during isel and immediately // Pseudo-registers: Used as placeholders during isel and immediately
// replaced, never seeing the verifier. // replaced, never seeing the verifier.
def PRIVATE_RSRC_REG : SIReg<"private_rsrc", 0>; def PRIVATE_RSRC_REG : SIReg<"private_rsrc", 0>;
def FP_REG : SIReg<"fp", 0>; def FP_REG : SIReg<"fp", 0>;
Show All 36 Lines
// Encoding changes between subtarget generations. // Encoding changes between subtarget generations.
// See also Utils/AMDGPUBaseInfo.cpp MAP_REG2REG. // See also Utils/AMDGPUBaseInfo.cpp MAP_REG2REG.
defm M0_gfxpre11 : SIRegLoHi16 <"m0", 124>; defm M0_gfxpre11 : SIRegLoHi16 <"m0", 124>;
defm M0_gfx11plus : SIRegLoHi16 <"m0", 125>; defm M0_gfx11plus : SIRegLoHi16 <"m0", 125>;
defm M0 : SIRegLoHi16 <"m0", 0>; defm M0 : SIRegLoHi16 <"m0", 0>;
defm SGPR_NULL_gfxpre11 : SIRegLoHi16 <"null", 125>; defm SGPR_NULL_gfxpre11 : SIRegLoHi16 <"null", 125>;
defm SGPR_NULL_gfx11plus : SIRegLoHi16 <"null", 124>; defm SGPR_NULL_gfx11plus : SIRegLoHi16 <"null", 124>;
defm SGPR_NULL : SIRegLoHi16 <"null", 0>; defm SGPR_NULL : SIRegLoHi16Const <"null", 0>;
defm SGPR_NULL_HI : SIRegLoHi16 <"", 0>; defm SGPR_NULL_HI : SIRegLoHi16Const <"", 0>;
def SGPR_NULL64 : def SGPR_NULL64 :
RegisterWithSubRegs<"null", [SGPR_NULL, SGPR_NULL_HI]> { RegisterWithSubRegs<"null", [SGPR_NULL, SGPR_NULL_HI]> {
let Namespace = "AMDGPU"; let Namespace = "AMDGPU";
let SubRegIndices = [sub0, sub1]; let SubRegIndices = [sub0, sub1];
let HWEncoding = SGPR_NULL.HWEncoding; let HWEncoding = SGPR_NULL.HWEncoding;
let isConstant = true;
} }
defm SRC_SHARED_BASE : SIRegLoHi16<"src_shared_base", 235>; defm SRC_SHARED_BASE : SIRegLoHi16Const<"src_shared_base", 235>;
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let ... in would avoid the need to mess with the multiclasses but that's a matter of taste for AMDGPU maintainers

jrtc27: let ... in would avoid the need to mess with the multiclasses but that's a matter of taste for…
defm SRC_SHARED_LIMIT : SIRegLoHi16<"src_shared_limit", 236>; defm SRC_SHARED_LIMIT : SIRegLoHi16Const<"src_shared_limit", 236>;
defm SRC_PRIVATE_BASE : SIRegLoHi16<"src_private_base", 237>; defm SRC_PRIVATE_BASE : SIRegLoHi16Const<"src_private_base", 237>;
defm SRC_PRIVATE_LIMIT : SIRegLoHi16<"src_private_limit", 238>; defm SRC_PRIVATE_LIMIT : SIRegLoHi16Const<"src_private_limit", 238>;
defm SRC_POPS_EXITING_WAVE_ID : SIRegLoHi16<"src_pops_exiting_wave_id", 239>; defm SRC_POPS_EXITING_WAVE_ID : SIRegLoHi16<"src_pops_exiting_wave_id", 239>;
// Not addressable // Not addressable
def MODE : SIReg <"mode", 0>; def MODE : SIReg <"mode", 0>;
def LDS_DIRECT : SIReg <"src_lds_direct", 254> { def LDS_DIRECT : SIReg <"src_lds_direct", 254> {
// There is no physical register corresponding to this. This is an // There is no physical register corresponding to this. This is an
// encoding value in a source field, which will ultimately trigger a // encoding value in a source field, which will ultimately trigger a
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