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llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
| Show First 20 Lines • Show All 3,081 Lines • ▼ Show 20 Lines | SIRegisterInfo::getProperlyAlignedRC(const TargetRegisterClass *RC) const { | ||||
| return RC; | return RC; | ||||
| } | } | ||||
| bool SIRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const { | bool SIRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const { | ||||
| switch (PhysReg) { | switch (PhysReg) { | ||||
| case AMDGPU::SGPR_NULL: | case AMDGPU::SGPR_NULL: | ||||
| case AMDGPU::SGPR_NULL64: | case AMDGPU::SGPR_NULL64: | ||||
| case AMDGPU::SGPR_NULL_HI: | |||||
| case AMDGPU::SRC_SHARED_BASE: | case AMDGPU::SRC_SHARED_BASE: | ||||
| case AMDGPU::SRC_PRIVATE_BASE: | case AMDGPU::SRC_PRIVATE_BASE: | ||||
| case AMDGPU::SRC_SHARED_LIMIT: | case AMDGPU::SRC_SHARED_LIMIT: | ||||
| case AMDGPU::SRC_PRIVATE_LIMIT: | case AMDGPU::SRC_PRIVATE_LIMIT: | ||||
| return true; | return true; | ||||
| default: | default: | ||||
| return false; | return false; | ||||
| } | } | ||||
| Show All 18 Lines | |||||