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llvm/lib/Target/AArch64/AArch64RegisterInfo.td
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| def W24 : AArch64Reg<24, "w24">, DwarfRegNum<[24]>; | def W24 : AArch64Reg<24, "w24">, DwarfRegNum<[24]>; | ||||
| def W25 : AArch64Reg<25, "w25">, DwarfRegNum<[25]>; | def W25 : AArch64Reg<25, "w25">, DwarfRegNum<[25]>; | ||||
| def W26 : AArch64Reg<26, "w26">, DwarfRegNum<[26]>; | def W26 : AArch64Reg<26, "w26">, DwarfRegNum<[26]>; | ||||
| def W27 : AArch64Reg<27, "w27">, DwarfRegNum<[27]>; | def W27 : AArch64Reg<27, "w27">, DwarfRegNum<[27]>; | ||||
| def W28 : AArch64Reg<28, "w28">, DwarfRegNum<[28]>; | def W28 : AArch64Reg<28, "w28">, DwarfRegNum<[28]>; | ||||
| def W29 : AArch64Reg<29, "w29">, DwarfRegNum<[29]>; | def W29 : AArch64Reg<29, "w29">, DwarfRegNum<[29]>; | ||||
| def W30 : AArch64Reg<30, "w30">, DwarfRegNum<[30]>; | def W30 : AArch64Reg<30, "w30">, DwarfRegNum<[30]>; | ||||
| def WSP : AArch64Reg<31, "wsp">, DwarfRegNum<[31]>; | def WSP : AArch64Reg<31, "wsp">, DwarfRegNum<[31]>; | ||||
| def WZR : AArch64Reg<31, "wzr">, DwarfRegAlias<WSP>; | def WZR : AArch64Reg<31, "wzr">, DwarfRegAlias<WSP> { let isConstant = true; } | ||||
| let SubRegIndices = [sub_32] in { | let SubRegIndices = [sub_32] in { | ||||
| def X0 : AArch64Reg<0, "x0", [W0]>, DwarfRegAlias<W0>; | def X0 : AArch64Reg<0, "x0", [W0]>, DwarfRegAlias<W0>; | ||||
| def X1 : AArch64Reg<1, "x1", [W1]>, DwarfRegAlias<W1>; | def X1 : AArch64Reg<1, "x1", [W1]>, DwarfRegAlias<W1>; | ||||
| def X2 : AArch64Reg<2, "x2", [W2]>, DwarfRegAlias<W2>; | def X2 : AArch64Reg<2, "x2", [W2]>, DwarfRegAlias<W2>; | ||||
| def X3 : AArch64Reg<3, "x3", [W3]>, DwarfRegAlias<W3>; | def X3 : AArch64Reg<3, "x3", [W3]>, DwarfRegAlias<W3>; | ||||
| def X4 : AArch64Reg<4, "x4", [W4]>, DwarfRegAlias<W4>; | def X4 : AArch64Reg<4, "x4", [W4]>, DwarfRegAlias<W4>; | ||||
| def X5 : AArch64Reg<5, "x5", [W5]>, DwarfRegAlias<W5>; | def X5 : AArch64Reg<5, "x5", [W5]>, DwarfRegAlias<W5>; | ||||
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| def X24 : AArch64Reg<24, "x24", [W24]>, DwarfRegAlias<W24>; | def X24 : AArch64Reg<24, "x24", [W24]>, DwarfRegAlias<W24>; | ||||
| def X25 : AArch64Reg<25, "x25", [W25]>, DwarfRegAlias<W25>; | def X25 : AArch64Reg<25, "x25", [W25]>, DwarfRegAlias<W25>; | ||||
| def X26 : AArch64Reg<26, "x26", [W26]>, DwarfRegAlias<W26>; | def X26 : AArch64Reg<26, "x26", [W26]>, DwarfRegAlias<W26>; | ||||
| def X27 : AArch64Reg<27, "x27", [W27]>, DwarfRegAlias<W27>; | def X27 : AArch64Reg<27, "x27", [W27]>, DwarfRegAlias<W27>; | ||||
| def X28 : AArch64Reg<28, "x28", [W28]>, DwarfRegAlias<W28>; | def X28 : AArch64Reg<28, "x28", [W28]>, DwarfRegAlias<W28>; | ||||
| def FP : AArch64Reg<29, "x29", [W29]>, DwarfRegAlias<W29>; | def FP : AArch64Reg<29, "x29", [W29]>, DwarfRegAlias<W29>; | ||||
| def LR : AArch64Reg<30, "x30", [W30]>, DwarfRegAlias<W30>; | def LR : AArch64Reg<30, "x30", [W30]>, DwarfRegAlias<W30>; | ||||
| def SP : AArch64Reg<31, "sp", [WSP]>, DwarfRegAlias<WSP>; | def SP : AArch64Reg<31, "sp", [WSP]>, DwarfRegAlias<WSP>; | ||||
| def XZR : AArch64Reg<31, "xzr", [WZR]>, DwarfRegAlias<WSP>; | def XZR : AArch64Reg<31, "xzr", [WZR]>, DwarfRegAlias<WSP> { let isConstant = true; } | ||||
| } | } | ||||
| // Condition code register. | // Condition code register. | ||||
| def NZCV : AArch64Reg<0, "nzcv">; | def NZCV : AArch64Reg<0, "nzcv">; | ||||
| // First fault status register | // First fault status register | ||||
| def FFR : AArch64Reg<0, "ffr">, DwarfRegNum<[47]>; | def FFR : AArch64Reg<0, "ffr">, DwarfRegNum<[47]>; | ||||
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