Page MenuHomePhabricator

Please use GitHub pull requests for new patches. Avoid migrating existing patches. Phabricator shutdown timeline

Differential D129066 Diff 449950 llvm/test/CodeGen/AArch64/complex-arithmetic-f64-add.ll

Changeset View

Standalone View

View Options

llvm/test/CodeGen/AArch64/complex-arithmetic-f64-add.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s ; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s
target triple = "aarch64-arm-none-eabi" target triple = "aarch64-arm-none-eabi"
define <2 x double> @complex_add_v2f64(<2 x double> %a, <2 x double> %b) { define <2 x double> @complex_add_v2f64(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: complex_add_v2f64: ; CHECK-LABEL: complex_add_v2f64:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: fcadd v0.2d, v1.2d, v0.2d, #90
; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-NEXT: fsub d1, d1, d2
; CHECK-NEXT: fadd d0, d3, d0
; CHECK-NEXT: mov v1.d[1], v0.d[0]
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a.real = shufflevector <2 x double> %a, <2 x double> zeroinitializer, <1 x i32> <i32 0> %a.real = shufflevector <2 x double> %a, <2 x double> zeroinitializer, <1 x i32> <i32 0>
%a.imag = shufflevector <2 x double> %a, <2 x double> zeroinitializer, <1 x i32> <i32 1> %a.imag = shufflevector <2 x double> %a, <2 x double> zeroinitializer, <1 x i32> <i32 1>
%b.real = shufflevector <2 x double> %b, <2 x double> zeroinitializer, <1 x i32> <i32 0> %b.real = shufflevector <2 x double> %b, <2 x double> zeroinitializer, <1 x i32> <i32 0>
%b.imag = shufflevector <2 x double> %b, <2 x double> zeroinitializer, <1 x i32> <i32 1> %b.imag = shufflevector <2 x double> %b, <2 x double> zeroinitializer, <1 x i32> <i32 1>
%0 = fsub fast <1 x double> %b.real, %a.imag %0 = fsub fast <1 x double> %b.real, %a.imag
%1 = fadd fast <1 x double> %b.imag, %a.real %1 = fadd fast <1 x double> %b.imag, %a.real
%interleaved.vec = shufflevector <1 x double> %0, <1 x double> %1, <2 x i32> <i32 0, i32 1> %interleaved.vec = shufflevector <1 x double> %0, <1 x double> %1, <2 x i32> <i32 0, i32 1>
ret <2 x double> %interleaved.vec ret <2 x double> %interleaved.vec
} }
define <4 x double> @complex_add_v4f64(<4 x double> %a, <4 x double> %b) { define <4 x double> @complex_add_v4f64(<4 x double> %a, <4 x double> %b) {
; CHECK-LABEL: complex_add_v4f64: ; CHECK-LABEL: complex_add_v4f64:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: zip1 v4.2d, v2.2d, v3.2d ; CHECK-NEXT: fcadd v0.2d, v2.2d, v0.2d, #90
; CHECK-NEXT: zip1 v5.2d, v0.2d, v1.2d ; CHECK-NEXT: fcadd v1.2d, v3.2d, v1.2d, #90
; CHECK-NEXT: zip2 v0.2d, v0.2d, v1.2d
; CHECK-NEXT: zip2 v1.2d, v2.2d, v3.2d
; CHECK-NEXT: fsub v2.2d, v4.2d, v0.2d
; CHECK-NEXT: fadd v1.2d, v1.2d, v5.2d
; CHECK-NEXT: zip1 v0.2d, v2.2d, v1.2d
; CHECK-NEXT: zip2 v1.2d, v2.2d, v1.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a.real = shufflevector <4 x double> %a, <4 x double> zeroinitializer, <2 x i32> <i32 0, i32 2> %a.real = shufflevector <4 x double> %a, <4 x double> zeroinitializer, <2 x i32> <i32 0, i32 2>
%a.imag = shufflevector <4 x double> %a, <4 x double> zeroinitializer, <2 x i32> <i32 1, i32 3> %a.imag = shufflevector <4 x double> %a, <4 x double> zeroinitializer, <2 x i32> <i32 1, i32 3>
%b.real = shufflevector <4 x double> %b, <4 x double> zeroinitializer, <2 x i32> <i32 0, i32 2> %b.real = shufflevector <4 x double> %b, <4 x double> zeroinitializer, <2 x i32> <i32 0, i32 2>
%b.imag = shufflevector <4 x double> %b, <4 x double> zeroinitializer, <2 x i32> <i32 1, i32 3> %b.imag = shufflevector <4 x double> %b, <4 x double> zeroinitializer, <2 x i32> <i32 1, i32 3>
%0 = fsub fast <2 x double> %b.real, %a.imag %0 = fsub fast <2 x double> %b.real, %a.imag
%1 = fadd fast <2 x double> %b.imag, %a.real %1 = fadd fast <2 x double> %b.imag, %a.real
%interleaved.vec = shufflevector <2 x double> %0, <2 x double> %1, <4 x i32> <i32 0, i32 2, i32 1, i32 3> %interleaved.vec = shufflevector <2 x double> %0, <2 x double> %1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
ret <4 x double> %interleaved.vec ret <4 x double> %interleaved.vec
} }
define <8 x double> @complex_add_v8f64(<8 x double> %a, <8 x double> %b) { define <8 x double> @complex_add_v8f64(<8 x double> %a, <8 x double> %b) {
; CHECK-LABEL: complex_add_v8f64: ; CHECK-LABEL: complex_add_v8f64:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: zip1 v16.2d, v4.2d, v5.2d ; CHECK-NEXT: fcadd v2.2d, v6.2d, v2.2d, #90
; CHECK-NEXT: zip1 v17.2d, v2.2d, v3.2d ; CHECK-NEXT: fcadd v0.2d, v4.2d, v0.2d, #90
; CHECK-NEXT: zip1 v18.2d, v0.2d, v1.2d ; CHECK-NEXT: fcadd v1.2d, v5.2d, v1.2d, #90
; CHECK-NEXT: zip2 v0.2d, v0.2d, v1.2d ; CHECK-NEXT: fcadd v3.2d, v7.2d, v3.2d, #90
; CHECK-NEXT: zip2 v1.2d, v2.2d, v3.2d
; CHECK-NEXT: zip2 v2.2d, v4.2d, v5.2d
; CHECK-NEXT: zip1 v3.2d, v6.2d, v7.2d
; CHECK-NEXT: zip2 v4.2d, v6.2d, v7.2d
; CHECK-NEXT: fsub v5.2d, v16.2d, v0.2d
; CHECK-NEXT: fadd v2.2d, v2.2d, v18.2d
; CHECK-NEXT: fsub v3.2d, v3.2d, v1.2d
; CHECK-NEXT: fadd v4.2d, v4.2d, v17.2d
; CHECK-NEXT: zip1 v0.2d, v5.2d, v2.2d
; CHECK-NEXT: zip2 v1.2d, v5.2d, v2.2d
; CHECK-NEXT: zip1 v2.2d, v3.2d, v4.2d
; CHECK-NEXT: zip2 v3.2d, v3.2d, v4.2d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a.real = shufflevector <8 x double> %a, <8 x double> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %a.real = shufflevector <8 x double> %a, <8 x double> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%a.imag = shufflevector <8 x double> %a, <8 x double> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %a.imag = shufflevector <8 x double> %a, <8 x double> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%b.real = shufflevector <8 x double> %b, <8 x double> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %b.real = shufflevector <8 x double> %b, <8 x double> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%b.imag = shufflevector <8 x double> %b, <8 x double> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %b.imag = shufflevector <8 x double> %b, <8 x double> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%0 = fsub fast <4 x double> %b.real, %a.imag %0 = fsub fast <4 x double> %b.real, %a.imag
%1 = fadd fast <4 x double> %b.imag, %a.real %1 = fadd fast <4 x double> %b.imag, %a.real
%interleaved.vec = shufflevector <4 x double> %0, <4 x double> %1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> %interleaved.vec = shufflevector <4 x double> %0, <4 x double> %1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
ret <8 x double> %interleaved.vec ret <8 x double> %interleaved.vec
} }