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Differential D129066 Diff 449950 llvm/test/CodeGen/AArch64/complex-arithmetic-f16-add.ll

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llvm/test/CodeGen/AArch64/complex-arithmetic-f16-add.ll

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%1 = fadd fast <1 x half> %b.imag, %a.real %1 = fadd fast <1 x half> %b.imag, %a.real
%interleaved.vec = shufflevector <1 x half> %0, <1 x half> %1, <2 x i32> <i32 0, i32 1> %interleaved.vec = shufflevector <1 x half> %0, <1 x half> %1, <2 x i32> <i32 0, i32 1>
ret <2 x half> %interleaved.vec ret <2 x half> %interleaved.vec
} }
define <4 x half> @complex_add_v4f16(<4 x half> %a, <4 x half> %b) { define <4 x half> @complex_add_v4f16(<4 x half> %a, <4 x half> %b) {
; CHECK-LABEL: complex_add_v4f16: ; CHECK-LABEL: complex_add_v4f16:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: uzp1 v2.4h, v0.4h, v0.4h ; CHECK-NEXT: fcadd v0.4h, v1.4h, v0.4h, #90
; CHECK-NEXT: uzp2 v0.4h, v0.4h, v0.4h
; CHECK-NEXT: uzp1 v3.4h, v1.4h, v0.4h
; CHECK-NEXT: uzp2 v1.4h, v1.4h, v0.4h
; CHECK-NEXT: fsub v0.4h, v3.4h, v0.4h
; CHECK-NEXT: fadd v1.4h, v1.4h, v2.4h
; CHECK-NEXT: zip1 v0.4h, v0.4h, v1.4h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a.real = shufflevector <4 x half> %a, <4 x half> zeroinitializer, <2 x i32> <i32 0, i32 2> %a.real = shufflevector <4 x half> %a, <4 x half> zeroinitializer, <2 x i32> <i32 0, i32 2>
%a.imag = shufflevector <4 x half> %a, <4 x half> zeroinitializer, <2 x i32> <i32 1, i32 3> %a.imag = shufflevector <4 x half> %a, <4 x half> zeroinitializer, <2 x i32> <i32 1, i32 3>
%b.real = shufflevector <4 x half> %b, <4 x half> zeroinitializer, <2 x i32> <i32 0, i32 2> %b.real = shufflevector <4 x half> %b, <4 x half> zeroinitializer, <2 x i32> <i32 0, i32 2>
%b.imag = shufflevector <4 x half> %b, <4 x half> zeroinitializer, <2 x i32> <i32 1, i32 3> %b.imag = shufflevector <4 x half> %b, <4 x half> zeroinitializer, <2 x i32> <i32 1, i32 3>
%0 = fsub fast <2 x half> %b.real, %a.imag %0 = fsub fast <2 x half> %b.real, %a.imag
%1 = fadd fast <2 x half> %b.imag, %a.real %1 = fadd fast <2 x half> %b.imag, %a.real
%interleaved.vec = shufflevector <2 x half> %0, <2 x half> %1, <4 x i32> <i32 0, i32 2, i32 1, i32 3> %interleaved.vec = shufflevector <2 x half> %0, <2 x half> %1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
ret <4 x half> %interleaved.vec ret <4 x half> %interleaved.vec
} }
define <8 x half> @complex_add_v8f16(<8 x half> %a, <8 x half> %b) { define <8 x half> @complex_add_v8f16(<8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: complex_add_v8f16: ; CHECK-LABEL: complex_add_v8f16:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: fcadd v0.8h, v1.8h, v0.8h, #90
; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-NEXT: uzp1 v4.4h, v0.4h, v2.4h
; CHECK-NEXT: uzp2 v0.4h, v0.4h, v2.4h
; CHECK-NEXT: uzp1 v2.4h, v1.4h, v3.4h
; CHECK-NEXT: uzp2 v1.4h, v1.4h, v3.4h
; CHECK-NEXT: fsub v0.4h, v2.4h, v0.4h
; CHECK-NEXT: fadd v1.4h, v1.4h, v4.4h
; CHECK-NEXT: zip2 v2.4h, v0.4h, v1.4h
; CHECK-NEXT: zip1 v0.4h, v0.4h, v1.4h
; CHECK-NEXT: mov v0.d[1], v2.d[0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a.real = shufflevector <8 x half> %a, <8 x half> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %a.real = shufflevector <8 x half> %a, <8 x half> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%a.imag = shufflevector <8 x half> %a, <8 x half> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %a.imag = shufflevector <8 x half> %a, <8 x half> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%b.real = shufflevector <8 x half> %b, <8 x half> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %b.real = shufflevector <8 x half> %b, <8 x half> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%b.imag = shufflevector <8 x half> %b, <8 x half> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %b.imag = shufflevector <8 x half> %b, <8 x half> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%0 = fsub fast <4 x half> %b.real, %a.imag %0 = fsub fast <4 x half> %b.real, %a.imag
%1 = fadd fast <4 x half> %b.imag, %a.real %1 = fadd fast <4 x half> %b.imag, %a.real
%interleaved.vec = shufflevector <4 x half> %0, <4 x half> %1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> %interleaved.vec = shufflevector <4 x half> %0, <4 x half> %1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
ret <8 x half> %interleaved.vec ret <8 x half> %interleaved.vec
} }
define <16 x half> @complex_add_v16f16(<16 x half> %a, <16 x half> %b) { define <16 x half> @complex_add_v16f16(<16 x half> %a, <16 x half> %b) {
; CHECK-LABEL: complex_add_v16f16: ; CHECK-LABEL: complex_add_v16f16:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: uzp1 v4.8h, v2.8h, v3.8h ; CHECK-NEXT: fcadd v0.8h, v2.8h, v0.8h, #90
; CHECK-NEXT: uzp1 v5.8h, v0.8h, v1.8h ; CHECK-NEXT: fcadd v1.8h, v3.8h, v1.8h, #90
; CHECK-NEXT: uzp2 v0.8h, v0.8h, v1.8h
; CHECK-NEXT: uzp2 v1.8h, v2.8h, v3.8h
; CHECK-NEXT: fsub v2.8h, v4.8h, v0.8h
; CHECK-NEXT: fadd v1.8h, v1.8h, v5.8h
; CHECK-NEXT: zip1 v0.8h, v2.8h, v1.8h
; CHECK-NEXT: zip2 v1.8h, v2.8h, v1.8h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a.real = shufflevector <16 x half> %a, <16 x half> zeroinitializer, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> %a.real = shufflevector <16 x half> %a, <16 x half> zeroinitializer, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%a.imag = shufflevector <16 x half> %a, <16 x half> zeroinitializer, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> %a.imag = shufflevector <16 x half> %a, <16 x half> zeroinitializer, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%b.real = shufflevector <16 x half> %b, <16 x half> zeroinitializer, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> %b.real = shufflevector <16 x half> %b, <16 x half> zeroinitializer, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%b.imag = shufflevector <16 x half> %b, <16 x half> zeroinitializer, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> %b.imag = shufflevector <16 x half> %b, <16 x half> zeroinitializer, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%0 = fsub fast <8 x half> %b.real, %a.imag %0 = fsub fast <8 x half> %b.real, %a.imag
%1 = fadd fast <8 x half> %b.imag, %a.real %1 = fadd fast <8 x half> %b.imag, %a.real
%interleaved.vec = shufflevector <8 x half> %0, <8 x half> %1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> %interleaved.vec = shufflevector <8 x half> %0, <8 x half> %1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
ret <16 x half> %interleaved.vec ret <16 x half> %interleaved.vec
} }
define <32 x half> @complex_add_v32f16(<32 x half> %a, <32 x half> %b) { define <32 x half> @complex_add_v32f16(<32 x half> %a, <32 x half> %b) {
; CHECK-LABEL: complex_add_v32f16: ; CHECK-LABEL: complex_add_v32f16:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: uzp1 v16.8h, v4.8h, v5.8h ; CHECK-NEXT: fcadd v2.8h, v6.8h, v2.8h, #90
; CHECK-NEXT: uzp1 v17.8h, v2.8h, v3.8h ; CHECK-NEXT: fcadd v0.8h, v4.8h, v0.8h, #90
; CHECK-NEXT: uzp1 v18.8h, v0.8h, v1.8h ; CHECK-NEXT: fcadd v1.8h, v5.8h, v1.8h, #90
; CHECK-NEXT: uzp2 v0.8h, v0.8h, v1.8h ; CHECK-NEXT: fcadd v3.8h, v7.8h, v3.8h, #90
; CHECK-NEXT: uzp2 v1.8h, v2.8h, v3.8h
; CHECK-NEXT: uzp2 v2.8h, v4.8h, v5.8h
; CHECK-NEXT: uzp1 v3.8h, v6.8h, v7.8h
; CHECK-NEXT: uzp2 v4.8h, v6.8h, v7.8h
; CHECK-NEXT: fsub v5.8h, v16.8h, v0.8h
; CHECK-NEXT: fadd v2.8h, v2.8h, v18.8h
; CHECK-NEXT: fsub v3.8h, v3.8h, v1.8h
; CHECK-NEXT: fadd v4.8h, v4.8h, v17.8h
; CHECK-NEXT: zip1 v0.8h, v5.8h, v2.8h
; CHECK-NEXT: zip2 v1.8h, v5.8h, v2.8h
; CHECK-NEXT: zip1 v2.8h, v3.8h, v4.8h
; CHECK-NEXT: zip2 v3.8h, v3.8h, v4.8h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a.real = shufflevector <32 x half> %a, <32 x half> zeroinitializer, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> %a.real = shufflevector <32 x half> %a, <32 x half> zeroinitializer, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
%a.imag = shufflevector <32 x half> %a, <32 x half> zeroinitializer, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> %a.imag = shufflevector <32 x half> %a, <32 x half> zeroinitializer, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
%b.real = shufflevector <32 x half> %b, <32 x half> zeroinitializer, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> %b.real = shufflevector <32 x half> %b, <32 x half> zeroinitializer, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
%b.imag = shufflevector <32 x half> %b, <32 x half> zeroinitializer, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> %b.imag = shufflevector <32 x half> %b, <32 x half> zeroinitializer, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
%0 = fsub fast <16 x half> %b.real, %a.imag %0 = fsub fast <16 x half> %b.real, %a.imag
%1 = fadd fast <16 x half> %b.imag, %a.real %1 = fadd fast <16 x half> %b.imag, %a.real
%interleaved.vec = shufflevector <16 x half> %0, <16 x half> %1, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> %interleaved.vec = shufflevector <16 x half> %0, <16 x half> %1, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
ret <32 x half> %interleaved.vec ret <32 x half> %interleaved.vec
} }