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llvm/lib/Target/AArch64/AArch64ISelLowering.h
| Show First 20 Lines • Show All 795 Lines • ▼ Show 20 Lines | bool shouldTransformSignedTruncationCheck(EVT XVT, | ||||
| MVT KeptBitsVT = MVT::getIntegerVT(KeptBits); | MVT KeptBitsVT = MVT::getIntegerVT(KeptBits); | ||||
| return VTIsOk(XVT) && VTIsOk(KeptBitsVT); | return VTIsOk(XVT) && VTIsOk(KeptBitsVT); | ||||
| } | } | ||||
| bool preferIncOfAddToSubOfNot(EVT VT) const override; | bool preferIncOfAddToSubOfNot(EVT VT) const override; | ||||
| bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override; | bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override; | ||||
| bool isComplexDeinterleavingSupported() const override; | |||||
| bool isComplexDeinterleavingOperationSupported( | |||||
| ComplexDeinterleavingOperation Operation, Type *Ty) const override; | |||||
| Value * | |||||
| createComplexDeinterleavingIR(Instruction *I, | |||||
| ComplexDeinterleavingOperation OperationType, | |||||
| unsigned Rotation, Value *InputA, Value *InputB, | |||||
| Value *Accumulator = nullptr) const override; | |||||
| bool hasBitPreservingFPLogic(EVT VT) const override { | bool hasBitPreservingFPLogic(EVT VT) const override { | ||||
| // FIXME: Is this always true? It should be true for vectors at least. | // FIXME: Is this always true? It should be true for vectors at least. | ||||
| return VT == MVT::f32 || VT == MVT::f64; | return VT == MVT::f32 || VT == MVT::f64; | ||||
| } | } | ||||
| bool supportSplitCSR(MachineFunction *MF) const override { | bool supportSplitCSR(MachineFunction *MF) const override { | ||||
| return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && | return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && | ||||
| MF->getFunction().hasFnAttribute(Attribute::NoUnwind); | MF->getFunction().hasFnAttribute(Attribute::NoUnwind); | ||||
| ▲ Show 20 Lines • Show All 364 Lines • Show Last 20 Lines | |||||