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llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.cpp
| Show First 20 Lines • Show All 143 Lines • ▼ Show 20 Lines | bool isReallyAClobber(const Value *Ptr, MemoryDef *Def, AAResults *AA) { | ||||
| if (isa<FenceInst>(DefInst)) | if (isa<FenceInst>(DefInst)) | ||||
| return false; | return false; | ||||
| if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(DefInst)) { | if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(DefInst)) { | ||||
| switch (II->getIntrinsicID()) { | switch (II->getIntrinsicID()) { | ||||
| case Intrinsic::amdgcn_s_barrier: | case Intrinsic::amdgcn_s_barrier: | ||||
| case Intrinsic::amdgcn_wave_barrier: | case Intrinsic::amdgcn_wave_barrier: | ||||
| case Intrinsic::amdgcn_sched_barrier: | case Intrinsic::amdgcn_sched_barrier: | ||||
| case Intrinsic::amdgcn_sched_group_barrier: | |||||
| return false; | return false; | ||||
| default: | default: | ||||
| break; | break; | ||||
| } | } | ||||
| } | } | ||||
| // Ignore atomics not aliasing with the original load, any atomic is a | // Ignore atomics not aliasing with the original load, any atomic is a | ||||
| // universal MemoryDef from MSSA's point of view too, just like a fence. | // universal MemoryDef from MSSA's point of view too, just like a fence. | ||||
| ▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines | |||||