Changeset View
Changeset View
Standalone View
Standalone View
llvm/lib/Target/AMDGPU/SIInstructions.td
| Show First 20 Lines • Show All 323 Lines • ▼ Show 20 Lines | def SCHED_BARRIER : SPseudoInstSI<(outs), (ins i32imm:$mask), | ||||
| let mayLoad = 0; | let mayLoad = 0; | ||||
| let mayStore = 0; | let mayStore = 0; | ||||
| let isConvergent = 1; | let isConvergent = 1; | ||||
| let FixedSize = 1; | let FixedSize = 1; | ||||
| let Size = 0; | let Size = 0; | ||||
| let isMeta = 1; | let isMeta = 1; | ||||
| } | } | ||||
| def SCHED_GROUP_BARRIER : SPseudoInstSI< | |||||
| (outs), | |||||
| (ins i32imm:$mask, i32imm:$size, i32imm:$syncid), | |||||
| [(int_amdgcn_sched_group_barrier (i32 timm:$mask), (i32 timm:$size), (i32 timm:$syncid))]> { | |||||
| let SchedRW = []; | |||||
| let hasNoSchedulingInfo = 1; | |||||
| let hasSideEffects = 1; | |||||
| let mayLoad = 0; | |||||
| let mayStore = 0; | |||||
| let isConvergent = 1; | |||||
| let FixedSize = 1; | |||||
| let Size = 0; | |||||
| } | |||||
| // SI pseudo instructions. These are used by the CFG structurizer pass | // SI pseudo instructions. These are used by the CFG structurizer pass | ||||
| // and should be lowered to ISA instructions prior to codegen. | // and should be lowered to ISA instructions prior to codegen. | ||||
| let isTerminator = 1 in { | let isTerminator = 1 in { | ||||
| let OtherPredicates = [EnableLateCFGStructurize] in { | let OtherPredicates = [EnableLateCFGStructurize] in { | ||||
| def SI_NON_UNIFORM_BRCOND_PSEUDO : CFPseudoInstSI < | def SI_NON_UNIFORM_BRCOND_PSEUDO : CFPseudoInstSI < | ||||
| (outs), | (outs), | ||||
| ▲ Show 20 Lines • Show All 3,004 Lines • Show Last 20 Lines | |||||