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llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
| Show First 20 Lines • Show All 215 Lines • ▼ Show 20 Lines | if (MI->getOpcode() == AMDGPU::SCHED_BARRIER) { | ||||
| std::string HexString; | std::string HexString; | ||||
| raw_string_ostream HexStream(HexString); | raw_string_ostream HexStream(HexString); | ||||
| HexStream << format_hex(MI->getOperand(0).getImm(), 10, true); | HexStream << format_hex(MI->getOperand(0).getImm(), 10, true); | ||||
| OutStreamer->emitRawComment(" sched_barrier mask(" + HexString + ")"); | OutStreamer->emitRawComment(" sched_barrier mask(" + HexString + ")"); | ||||
| } | } | ||||
| return; | return; | ||||
| } | } | ||||
| if (MI->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER) { | |||||
| if (isVerbose()) { | |||||
| std::string HexString; | |||||
| raw_string_ostream HexStream(HexString); | |||||
| HexStream << format_hex(MI->getOperand(0).getImm(), 10, true); | |||||
| OutStreamer->emitRawComment( | |||||
| " sched_group_barrier mask(" + HexString + ") size(" + | |||||
| Twine(MI->getOperand(1).getImm()) + ") SyncID(" + | |||||
| Twine(MI->getOperand(2).getImm()) + ")"); | |||||
| } | |||||
| return; | |||||
| } | |||||
| if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) { | if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) { | ||||
| if (isVerbose()) | if (isVerbose()) | ||||
| OutStreamer->emitRawComment(" divergent unreachable"); | OutStreamer->emitRawComment(" divergent unreachable"); | ||||
| return; | return; | ||||
| } | } | ||||
| if (MI->isMetaInstruction()) { | if (MI->isMetaInstruction()) { | ||||
| if (isVerbose()) | if (isVerbose()) | ||||
| ▲ Show 20 Lines • Show All 62 Lines • Show Last 20 Lines | |||||