Page MenuHomePhabricator
Differential D128065 Diff 445500 llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll

Changeset View

Standalone View

View Options

llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll

Show First 20 Lines • Show All 155 Lines • ▼ Show 20 Lines
; VBITS_GE_256-NEXT: ucvtf z1.s, p0/m, z1.s ; VBITS_GE_256-NEXT: ucvtf z1.s, p0/m, z1.s
; VBITS_GE_256-NEXT: ucvtf z0.s, p0/m, z0.s ; VBITS_GE_256-NEXT: ucvtf z0.s, p0/m, z0.s
; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x1] ; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x1]
; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2] ; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]
; VBITS_GE_256-NEXT: ret ; VBITS_GE_256-NEXT: ret
; ;
; VBITS_GE_512-LABEL: ucvtf_v16i16_v16f32: ; VBITS_GE_512-LABEL: ucvtf_v16i16_v16f32:
; VBITS_GE_512: // %bb.0: ; VBITS_GE_512: // %bb.0:
; VBITS_GE_512-NEXT: ptrue p0.h, vl16
; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]
; VBITS_GE_512-NEXT: ptrue p0.s, vl16 ; VBITS_GE_512-NEXT: ptrue p0.s, vl16
; VBITS_GE_512-NEXT: uunpklo z0.s, z0.h ; VBITS_GE_512-NEXT: ld1h { z0.s }, p0/z, [x0]
; VBITS_GE_512-NEXT: ucvtf z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: ucvtf z0.s, p0/m, z0.s
; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1] ; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1]
; VBITS_GE_512-NEXT: ret ; VBITS_GE_512-NEXT: ret
%op1 = load <16 x i16>, <16 x i16>* %a %op1 = load <16 x i16>, <16 x i16>* %a
%res = uitofp <16 x i16> %op1 to <16 x float> %res = uitofp <16 x i16> %op1 to <16 x float>
store <16 x float> %res, <16 x float>* %b store <16 x float> %res, <16 x float>* %b
ret void ret void
} }
define void @ucvtf_v32i16_v32f32(<32 x i16>* %a, <32 x float>* %b) vscale_range(8,0) #0 { define void @ucvtf_v32i16_v32f32(<32 x i16>* %a, <32 x float>* %b) vscale_range(8,0) #0 {
; CHECK-LABEL: ucvtf_v32i16_v32f32: ; CHECK-LABEL: ucvtf_v32i16_v32f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h, vl32
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.s, vl32 ; CHECK-NEXT: ptrue p0.s, vl32
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s ; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s
; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: st1w { z0.s }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op1 = load <32 x i16>, <32 x i16>* %a %op1 = load <32 x i16>, <32 x i16>* %a
%res = uitofp <32 x i16> %op1 to <32 x float> %res = uitofp <32 x i16> %op1 to <32 x float>
store <32 x float> %res, <32 x float>* %b store <32 x float> %res, <32 x float>* %b
ret void ret void
} }
define void @ucvtf_v64i16_v64f32(<64 x i16>* %a, <64 x float>* %b) vscale_range(16,0) #0 { define void @ucvtf_v64i16_v64f32(<64 x i16>* %a, <64 x float>* %b) vscale_range(16,0) #0 {
; CHECK-LABEL: ucvtf_v64i16_v64f32: ; CHECK-LABEL: ucvtf_v64i16_v64f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h, vl64
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.s, vl64 ; CHECK-NEXT: ptrue p0.s, vl64
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s ; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s
; CHECK-NEXT: st1w { z0.s }, p0, [x1] ; CHECK-NEXT: st1w { z0.s }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op1 = load <64 x i16>, <64 x i16>* %a %op1 = load <64 x i16>, <64 x i16>* %a
%res = uitofp <64 x i16> %op1 to <64 x float> %res = uitofp <64 x i16> %op1 to <64 x float>
store <64 x float> %res, <64 x float>* %b store <64 x float> %res, <64 x float>* %b
ret void ret void
} }
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines; VBITS_GE_512-NEXT: ret
%res = uitofp <8 x i16> %op1 to <8 x double> %res = uitofp <8 x i16> %op1 to <8 x double>
store <8 x double> %res, <8 x double>* %b store <8 x double> %res, <8 x double>* %b
ret void ret void
} }
define void @ucvtf_v16i16_v16f64(<16 x i16>* %a, <16 x double>* %b) vscale_range(8,0) #0 { define void @ucvtf_v16i16_v16f64(<16 x i16>* %a, <16 x double>* %b) vscale_range(8,0) #0 {
; CHECK-LABEL: ucvtf_v16i16_v16f64: ; CHECK-LABEL: ucvtf_v16i16_v16f64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h, vl16
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.d, vl16 ; CHECK-NEXT: ptrue p0.d, vl16
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0]
; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d ; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d
; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: st1d { z0.d }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op1 = load <16 x i16>, <16 x i16>* %a %op1 = load <16 x i16>, <16 x i16>* %a
%res = uitofp <16 x i16> %op1 to <16 x double> %res = uitofp <16 x i16> %op1 to <16 x double>
store <16 x double> %res, <16 x double>* %b store <16 x double> %res, <16 x double>* %b
ret void ret void
} }
define void @ucvtf_v32i16_v32f64(<32 x i16>* %a, <32 x double>* %b) vscale_range(16,0) #0 { define void @ucvtf_v32i16_v32f64(<32 x i16>* %a, <32 x double>* %b) vscale_range(16,0) #0 {
; CHECK-LABEL: ucvtf_v32i16_v32f64: ; CHECK-LABEL: ucvtf_v32i16_v32f64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h, vl32
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.d, vl32 ; CHECK-NEXT: ptrue p0.d, vl32
; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0]
; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d ; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d
; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: st1d { z0.d }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op1 = load <32 x i16>, <32 x i16>* %a %op1 = load <32 x i16>, <32 x i16>* %a
%res = uitofp <32 x i16> %op1 to <32 x double> %res = uitofp <32 x i16> %op1 to <32 x double>
store <32 x double> %res, <32 x double>* %b store <32 x double> %res, <32 x double>* %b
ret void ret void
} }
▲ Show 20 Lines • Show All 255 Lines • ▼ Show 20 Lines
; VBITS_GE_256-NEXT: ucvtf z1.d, p0/m, z1.d ; VBITS_GE_256-NEXT: ucvtf z1.d, p0/m, z1.d
; VBITS_GE_256-NEXT: ucvtf z0.d, p0/m, z0.d ; VBITS_GE_256-NEXT: ucvtf z0.d, p0/m, z0.d
; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x1] ; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x1]
; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x1, x8, lsl #3] ; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x1, x8, lsl #3]
; VBITS_GE_256-NEXT: ret ; VBITS_GE_256-NEXT: ret
; ;
; VBITS_GE_512-LABEL: ucvtf_v8i32_v8f64: ; VBITS_GE_512-LABEL: ucvtf_v8i32_v8f64:
; VBITS_GE_512: // %bb.0: ; VBITS_GE_512: // %bb.0:
; VBITS_GE_512-NEXT: ptrue p0.s, vl8
; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]
; VBITS_GE_512-NEXT: ptrue p0.d, vl8 ; VBITS_GE_512-NEXT: ptrue p0.d, vl8
; VBITS_GE_512-NEXT: uunpklo z0.d, z0.s ; VBITS_GE_512-NEXT: ld1w { z0.d }, p0/z, [x0]
; VBITS_GE_512-NEXT: ucvtf z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: ucvtf z0.d, p0/m, z0.d
; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1] ; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1]
; VBITS_GE_512-NEXT: ret ; VBITS_GE_512-NEXT: ret
%op1 = load <8 x i32>, <8 x i32>* %a %op1 = load <8 x i32>, <8 x i32>* %a
%res = uitofp <8 x i32> %op1 to <8 x double> %res = uitofp <8 x i32> %op1 to <8 x double>
store <8 x double> %res, <8 x double>* %b store <8 x double> %res, <8 x double>* %b
ret void ret void
} }
define void @ucvtf_v16i32_v16f64(<16 x i32>* %a, <16 x double>* %b) vscale_range(8,0) #0 { define void @ucvtf_v16i32_v16f64(<16 x i32>* %a, <16 x double>* %b) vscale_range(8,0) #0 {
; CHECK-LABEL: ucvtf_v16i32_v16f64: ; CHECK-LABEL: ucvtf_v16i32_v16f64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s, vl16
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.d, vl16 ; CHECK-NEXT: ptrue p0.d, vl16
; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]
; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d ; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d
; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: st1d { z0.d }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op1 = load <16 x i32>, <16 x i32>* %a %op1 = load <16 x i32>, <16 x i32>* %a
%res = uitofp <16 x i32> %op1 to <16 x double> %res = uitofp <16 x i32> %op1 to <16 x double>
store <16 x double> %res, <16 x double>* %b store <16 x double> %res, <16 x double>* %b
ret void ret void
} }
define void @ucvtf_v32i32_v32f64(<32 x i32>* %a, <32 x double>* %b) vscale_range(16,0) #0 { define void @ucvtf_v32i32_v32f64(<32 x i32>* %a, <32 x double>* %b) vscale_range(16,0) #0 {
; CHECK-LABEL: ucvtf_v32i32_v32f64: ; CHECK-LABEL: ucvtf_v32i32_v32f64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s, vl32
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.d, vl32 ; CHECK-NEXT: ptrue p0.d, vl32
; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]
; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d ; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d
; CHECK-NEXT: st1d { z0.d }, p0, [x1] ; CHECK-NEXT: st1d { z0.d }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op1 = load <32 x i32>, <32 x i32>* %a %op1 = load <32 x i32>, <32 x i32>* %a
%res = uitofp <32 x i32> %op1 to <32 x double> %res = uitofp <32 x i32> %op1 to <32 x double>
store <32 x double> %res, <32 x double>* %b store <32 x double> %res, <32 x double>* %b
ret void ret void
} }
▲ Show 20 Lines • Show All 1,264 Lines • Show Last 20 Lines