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Differential D128065 Diff 445500 llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll

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llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll

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; VBITS_GE_256-NEXT: splice z1.h, p0, z1.h, z0.h ; VBITS_GE_256-NEXT: splice z1.h, p0, z1.h, z0.h
; VBITS_GE_256-NEXT: ptrue p0.h, vl16 ; VBITS_GE_256-NEXT: ptrue p0.h, vl16
; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x1] ; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x1]
; VBITS_GE_256-NEXT: ret ; VBITS_GE_256-NEXT: ret
; ;
; VBITS_GE_512-LABEL: fcvtzu_v16f32_v16i16: ; VBITS_GE_512-LABEL: fcvtzu_v16f32_v16i16:
; VBITS_GE_512: // %bb.0: ; VBITS_GE_512: // %bb.0:
; VBITS_GE_512-NEXT: ptrue p0.s, vl16 ; VBITS_GE_512-NEXT: ptrue p0.s, vl16
; VBITS_GE_512-NEXT: ptrue p1.s
; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0] ; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]
; VBITS_GE_512-NEXT: ptrue p0.s ; VBITS_GE_512-NEXT: fcvtzu z0.s, p1/m, z0.s
; VBITS_GE_512-NEXT: fcvtzu z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1h { z0.s }, p0, [x1]
; VBITS_GE_512-NEXT: ptrue p0.h, vl16
; VBITS_GE_512-NEXT: uzp1 z0.h, z0.h, z0.h
; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1]
; VBITS_GE_512-NEXT: ret ; VBITS_GE_512-NEXT: ret
%op1 = load <16 x float>, <16 x float>* %a %op1 = load <16 x float>, <16 x float>* %a
%res = fptoui <16 x float> %op1 to <16 x i16> %res = fptoui <16 x float> %op1 to <16 x i16>
store <16 x i16> %res, <16 x i16>* %b store <16 x i16> %res, <16 x i16>* %b
ret void ret void
} }
define void @fcvtzu_v32f32_v32i16(<32 x float>* %a, <32 x i16>* %b) vscale_range(8,0) #0 { define void @fcvtzu_v32f32_v32i16(<32 x float>* %a, <32 x i16>* %b) vscale_range(8,0) #0 {
; CHECK-LABEL: fcvtzu_v32f32_v32i16: ; CHECK-LABEL: fcvtzu_v32f32_v32i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s, vl32 ; CHECK-NEXT: ptrue p0.s, vl32
; CHECK-NEXT: ptrue p1.s
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: fcvtzu z0.s, p1/m, z0.s
; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s ; CHECK-NEXT: st1h { z0.s }, p0, [x1]
; CHECK-NEXT: ptrue p0.h, vl32
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: st1h { z0.h }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op1 = load <32 x float>, <32 x float>* %a %op1 = load <32 x float>, <32 x float>* %a
%res = fptoui <32 x float> %op1 to <32 x i16> %res = fptoui <32 x float> %op1 to <32 x i16>
store <32 x i16> %res, <32 x i16>* %b store <32 x i16> %res, <32 x i16>* %b
ret void ret void
} }
define void @fcvtzu_v64f32_v64i16(<64 x float>* %a, <64 x i16>* %b) vscale_range(16,0) #0 { define void @fcvtzu_v64f32_v64i16(<64 x float>* %a, <64 x i16>* %b) vscale_range(16,0) #0 {
; CHECK-LABEL: fcvtzu_v64f32_v64i16: ; CHECK-LABEL: fcvtzu_v64f32_v64i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s, vl64 ; CHECK-NEXT: ptrue p0.s, vl64
; CHECK-NEXT: ptrue p1.s
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: fcvtzu z0.s, p1/m, z0.s
; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s ; CHECK-NEXT: st1h { z0.s }, p0, [x1]
; CHECK-NEXT: ptrue p0.h, vl64
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: st1h { z0.h }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op1 = load <64 x float>, <64 x float>* %a %op1 = load <64 x float>, <64 x float>* %a
%res = fptoui <64 x float> %op1 to <64 x i16> %res = fptoui <64 x float> %op1 to <64 x i16>
store <64 x i16> %res, <64 x i16>* %b store <64 x i16> %res, <64 x i16>* %b
ret void ret void
} }
; ;
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%res = fptoui <8 x double> %op1 to <8 x i16> %res = fptoui <8 x double> %op1 to <8 x i16>
ret <8 x i16> %res ret <8 x i16> %res
} }
define void @fcvtzu_v16f64_v16i16(<16 x double>* %a, <16 x i16>* %b) vscale_range(8,0) #0 { define void @fcvtzu_v16f64_v16i16(<16 x double>* %a, <16 x i16>* %b) vscale_range(8,0) #0 {
; CHECK-LABEL: fcvtzu_v16f64_v16i16: ; CHECK-LABEL: fcvtzu_v16f64_v16i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl16 ; CHECK-NEXT: ptrue p0.d, vl16
; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzu z0.d, p1/m, z0.d
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d ; CHECK-NEXT: st1h { z0.d }, p0, [x1]
; CHECK-NEXT: ptrue p0.h, vl16
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: st1h { z0.h }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op1 = load <16 x double>, <16 x double>* %a %op1 = load <16 x double>, <16 x double>* %a
%res = fptoui <16 x double> %op1 to <16 x i16> %res = fptoui <16 x double> %op1 to <16 x i16>
store <16 x i16> %res, <16 x i16>* %b store <16 x i16> %res, <16 x i16>* %b
ret void ret void
} }
define void @fcvtzu_v32f64_v32i16(<32 x double>* %a, <32 x i16>* %b) vscale_range(16,0) #0 { define void @fcvtzu_v32f64_v32i16(<32 x double>* %a, <32 x i16>* %b) vscale_range(16,0) #0 {
; CHECK-LABEL: fcvtzu_v32f64_v32i16: ; CHECK-LABEL: fcvtzu_v32f64_v32i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl32 ; CHECK-NEXT: ptrue p0.d, vl32
; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzu z0.d, p1/m, z0.d
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d ; CHECK-NEXT: st1h { z0.d }, p0, [x1]
; CHECK-NEXT: ptrue p0.h, vl32
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: st1h { z0.h }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op1 = load <32 x double>, <32 x double>* %a %op1 = load <32 x double>, <32 x double>* %a
%res = fptoui <32 x double> %op1 to <32 x i16> %res = fptoui <32 x double> %op1 to <32 x i16>
store <32 x i16> %res, <32 x i16>* %b store <32 x i16> %res, <32 x i16>* %b
ret void ret void
} }
; ;
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; VBITS_GE_256-NEXT: splice z1.s, p0, z1.s, z0.s ; VBITS_GE_256-NEXT: splice z1.s, p0, z1.s, z0.s
; VBITS_GE_256-NEXT: ptrue p0.s, vl8 ; VBITS_GE_256-NEXT: ptrue p0.s, vl8
; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x1] ; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x1]
; VBITS_GE_256-NEXT: ret ; VBITS_GE_256-NEXT: ret
; ;
; VBITS_GE_512-LABEL: fcvtzu_v8f64_v8i32: ; VBITS_GE_512-LABEL: fcvtzu_v8f64_v8i32:
; VBITS_GE_512: // %bb.0: ; VBITS_GE_512: // %bb.0:
; VBITS_GE_512-NEXT: ptrue p0.d, vl8 ; VBITS_GE_512-NEXT: ptrue p0.d, vl8
; VBITS_GE_512-NEXT: ptrue p1.d
; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0] ; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]
; VBITS_GE_512-NEXT: ptrue p0.d ; VBITS_GE_512-NEXT: fcvtzu z0.d, p1/m, z0.d
; VBITS_GE_512-NEXT: fcvtzu z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1w { z0.d }, p0, [x1]
; VBITS_GE_512-NEXT: ptrue p0.s, vl8
; VBITS_GE_512-NEXT: uzp1 z0.s, z0.s, z0.s
; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1]
; VBITS_GE_512-NEXT: ret ; VBITS_GE_512-NEXT: ret
%op1 = load <8 x double>, <8 x double>* %a %op1 = load <8 x double>, <8 x double>* %a
%res = fptoui <8 x double> %op1 to <8 x i32> %res = fptoui <8 x double> %op1 to <8 x i32>
store <8 x i32> %res, <8 x i32>* %b store <8 x i32> %res, <8 x i32>* %b
ret void ret void
} }
define void @fcvtzu_v16f64_v16i32(<16 x double>* %a, <16 x i32>* %b) vscale_range(8,0) #0 { define void @fcvtzu_v16f64_v16i32(<16 x double>* %a, <16 x i32>* %b) vscale_range(8,0) #0 {
; CHECK-LABEL: fcvtzu_v16f64_v16i32: ; CHECK-LABEL: fcvtzu_v16f64_v16i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl16 ; CHECK-NEXT: ptrue p0.d, vl16
; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzu z0.d, p1/m, z0.d
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d ; CHECK-NEXT: st1w { z0.d }, p0, [x1]
; CHECK-NEXT: ptrue p0.s, vl16
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: st1w { z0.s }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op1 = load <16 x double>, <16 x double>* %a %op1 = load <16 x double>, <16 x double>* %a
%res = fptoui <16 x double> %op1 to <16 x i32> %res = fptoui <16 x double> %op1 to <16 x i32>
store <16 x i32> %res, <16 x i32>* %b store <16 x i32> %res, <16 x i32>* %b
ret void ret void
} }
define void @fcvtzu_v32f64_v32i32(<32 x double>* %a, <32 x i32>* %b) vscale_range(16,0) #0 { define void @fcvtzu_v32f64_v32i32(<32 x double>* %a, <32 x i32>* %b) vscale_range(16,0) #0 {
; CHECK-LABEL: fcvtzu_v32f64_v32i32: ; CHECK-LABEL: fcvtzu_v32f64_v32i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl32 ; CHECK-NEXT: ptrue p0.d, vl32
; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzu z0.d, p1/m, z0.d
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d ; CHECK-NEXT: st1w { z0.d }, p0, [x1]
; CHECK-NEXT: ptrue p0.s, vl32
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: st1w { z0.s }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op1 = load <32 x double>, <32 x double>* %a %op1 = load <32 x double>, <32 x double>* %a
%res = fptoui <32 x double> %op1 to <32 x i32> %res = fptoui <32 x double> %op1 to <32 x i32>
store <32 x i32> %res, <32 x i32>* %b store <32 x i32> %res, <32 x i32>* %b
ret void ret void
} }
; ;
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; VBITS_GE_256-NEXT: splice z1.h, p0, z1.h, z0.h ; VBITS_GE_256-NEXT: splice z1.h, p0, z1.h, z0.h
; VBITS_GE_256-NEXT: ptrue p0.h, vl16 ; VBITS_GE_256-NEXT: ptrue p0.h, vl16
; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x1] ; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x1]
; VBITS_GE_256-NEXT: ret ; VBITS_GE_256-NEXT: ret
; ;
; VBITS_GE_512-LABEL: fcvtzs_v16f32_v16i16: ; VBITS_GE_512-LABEL: fcvtzs_v16f32_v16i16:
; VBITS_GE_512: // %bb.0: ; VBITS_GE_512: // %bb.0:
; VBITS_GE_512-NEXT: ptrue p0.s, vl16 ; VBITS_GE_512-NEXT: ptrue p0.s, vl16
; VBITS_GE_512-NEXT: ptrue p1.s
; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0] ; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]
; VBITS_GE_512-NEXT: ptrue p0.s ; VBITS_GE_512-NEXT: fcvtzs z0.s, p1/m, z0.s
; VBITS_GE_512-NEXT: fcvtzs z0.s, p0/m, z0.s ; VBITS_GE_512-NEXT: st1h { z0.s }, p0, [x1]
; VBITS_GE_512-NEXT: ptrue p0.h, vl16
; VBITS_GE_512-NEXT: uzp1 z0.h, z0.h, z0.h
; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1]
; VBITS_GE_512-NEXT: ret ; VBITS_GE_512-NEXT: ret
%op1 = load <16 x float>, <16 x float>* %a %op1 = load <16 x float>, <16 x float>* %a
%res = fptosi <16 x float> %op1 to <16 x i16> %res = fptosi <16 x float> %op1 to <16 x i16>
store <16 x i16> %res, <16 x i16>* %b store <16 x i16> %res, <16 x i16>* %b
ret void ret void
} }
define void @fcvtzs_v32f32_v32i16(<32 x float>* %a, <32 x i16>* %b) vscale_range(8,0) #0 { define void @fcvtzs_v32f32_v32i16(<32 x float>* %a, <32 x i16>* %b) vscale_range(8,0) #0 {
; CHECK-LABEL: fcvtzs_v32f32_v32i16: ; CHECK-LABEL: fcvtzs_v32f32_v32i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s, vl32 ; CHECK-NEXT: ptrue p0.s, vl32
; CHECK-NEXT: ptrue p1.s
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: fcvtzs z0.s, p1/m, z0.s
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s ; CHECK-NEXT: st1h { z0.s }, p0, [x1]
; CHECK-NEXT: ptrue p0.h, vl32
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: st1h { z0.h }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op1 = load <32 x float>, <32 x float>* %a %op1 = load <32 x float>, <32 x float>* %a
%res = fptosi <32 x float> %op1 to <32 x i16> %res = fptosi <32 x float> %op1 to <32 x i16>
store <32 x i16> %res, <32 x i16>* %b store <32 x i16> %res, <32 x i16>* %b
ret void ret void
} }
define void @fcvtzs_v64f32_v64i16(<64 x float>* %a, <64 x i16>* %b) vscale_range(16,0) #0 { define void @fcvtzs_v64f32_v64i16(<64 x float>* %a, <64 x i16>* %b) vscale_range(16,0) #0 {
; CHECK-LABEL: fcvtzs_v64f32_v64i16: ; CHECK-LABEL: fcvtzs_v64f32_v64i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s, vl64 ; CHECK-NEXT: ptrue p0.s, vl64
; CHECK-NEXT: ptrue p1.s
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: fcvtzs z0.s, p1/m, z0.s
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s ; CHECK-NEXT: st1h { z0.s }, p0, [x1]
; CHECK-NEXT: ptrue p0.h, vl64
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: st1h { z0.h }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op1 = load <64 x float>, <64 x float>* %a %op1 = load <64 x float>, <64 x float>* %a
%res = fptosi <64 x float> %op1 to <64 x i16> %res = fptosi <64 x float> %op1 to <64 x i16>
store <64 x i16> %res, <64 x i16>* %b store <64 x i16> %res, <64 x i16>* %b
ret void ret void
} }
; ;
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%res = fptosi <8 x double> %op1 to <8 x i16> %res = fptosi <8 x double> %op1 to <8 x i16>
ret <8 x i16> %res ret <8 x i16> %res
} }
define void @fcvtzs_v16f64_v16i16(<16 x double>* %a, <16 x i16>* %b) vscale_range(8,0) #0 { define void @fcvtzs_v16f64_v16i16(<16 x double>* %a, <16 x i16>* %b) vscale_range(8,0) #0 {
; CHECK-LABEL: fcvtzs_v16f64_v16i16: ; CHECK-LABEL: fcvtzs_v16f64_v16i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl16 ; CHECK-NEXT: ptrue p0.d, vl16
; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzs z0.d, p1/m, z0.d
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d ; CHECK-NEXT: st1h { z0.d }, p0, [x1]
; CHECK-NEXT: ptrue p0.h, vl16
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: st1h { z0.h }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op1 = load <16 x double>, <16 x double>* %a %op1 = load <16 x double>, <16 x double>* %a
%res = fptosi <16 x double> %op1 to <16 x i16> %res = fptosi <16 x double> %op1 to <16 x i16>
store <16 x i16> %res, <16 x i16>* %b store <16 x i16> %res, <16 x i16>* %b
ret void ret void
} }
define void @fcvtzs_v32f64_v32i16(<32 x double>* %a, <32 x i16>* %b) vscale_range(16,0) #0 { define void @fcvtzs_v32f64_v32i16(<32 x double>* %a, <32 x i16>* %b) vscale_range(16,0) #0 {
; CHECK-LABEL: fcvtzs_v32f64_v32i16: ; CHECK-LABEL: fcvtzs_v32f64_v32i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl32 ; CHECK-NEXT: ptrue p0.d, vl32
; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzs z0.d, p1/m, z0.d
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d ; CHECK-NEXT: st1h { z0.d }, p0, [x1]
; CHECK-NEXT: ptrue p0.h, vl32
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: st1h { z0.h }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op1 = load <32 x double>, <32 x double>* %a %op1 = load <32 x double>, <32 x double>* %a
%res = fptosi <32 x double> %op1 to <32 x i16> %res = fptosi <32 x double> %op1 to <32 x i16>
store <32 x i16> %res, <32 x i16>* %b store <32 x i16> %res, <32 x i16>* %b
ret void ret void
} }
; ;
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; VBITS_GE_256-NEXT: splice z1.s, p0, z1.s, z0.s ; VBITS_GE_256-NEXT: splice z1.s, p0, z1.s, z0.s
; VBITS_GE_256-NEXT: ptrue p0.s, vl8 ; VBITS_GE_256-NEXT: ptrue p0.s, vl8
; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x1] ; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x1]
; VBITS_GE_256-NEXT: ret ; VBITS_GE_256-NEXT: ret
; ;
; VBITS_GE_512-LABEL: fcvtzs_v8f64_v8i32: ; VBITS_GE_512-LABEL: fcvtzs_v8f64_v8i32:
; VBITS_GE_512: // %bb.0: ; VBITS_GE_512: // %bb.0:
; VBITS_GE_512-NEXT: ptrue p0.d, vl8 ; VBITS_GE_512-NEXT: ptrue p0.d, vl8
; VBITS_GE_512-NEXT: ptrue p1.d
; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0] ; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]
; VBITS_GE_512-NEXT: ptrue p0.d ; VBITS_GE_512-NEXT: fcvtzs z0.d, p1/m, z0.d
; VBITS_GE_512-NEXT: fcvtzs z0.d, p0/m, z0.d ; VBITS_GE_512-NEXT: st1w { z0.d }, p0, [x1]
; VBITS_GE_512-NEXT: ptrue p0.s, vl8
; VBITS_GE_512-NEXT: uzp1 z0.s, z0.s, z0.s
; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1]
; VBITS_GE_512-NEXT: ret ; VBITS_GE_512-NEXT: ret
%op1 = load <8 x double>, <8 x double>* %a %op1 = load <8 x double>, <8 x double>* %a
%res = fptosi <8 x double> %op1 to <8 x i32> %res = fptosi <8 x double> %op1 to <8 x i32>
store <8 x i32> %res, <8 x i32>* %b store <8 x i32> %res, <8 x i32>* %b
ret void ret void
} }
define void @fcvtzs_v16f64_v16i32(<16 x double>* %a, <16 x i32>* %b) vscale_range(8,0) #0 { define void @fcvtzs_v16f64_v16i32(<16 x double>* %a, <16 x i32>* %b) vscale_range(8,0) #0 {
; CHECK-LABEL: fcvtzs_v16f64_v16i32: ; CHECK-LABEL: fcvtzs_v16f64_v16i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl16 ; CHECK-NEXT: ptrue p0.d, vl16
; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzs z0.d, p1/m, z0.d
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d ; CHECK-NEXT: st1w { z0.d }, p0, [x1]
; CHECK-NEXT: ptrue p0.s, vl16
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: st1w { z0.s }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op1 = load <16 x double>, <16 x double>* %a %op1 = load <16 x double>, <16 x double>* %a
%res = fptosi <16 x double> %op1 to <16 x i32> %res = fptosi <16 x double> %op1 to <16 x i32>
store <16 x i32> %res, <16 x i32>* %b store <16 x i32> %res, <16 x i32>* %b
ret void ret void
} }
define void @fcvtzs_v32f64_v32i32(<32 x double>* %a, <32 x i32>* %b) vscale_range(16,0) #0 { define void @fcvtzs_v32f64_v32i32(<32 x double>* %a, <32 x i32>* %b) vscale_range(16,0) #0 {
; CHECK-LABEL: fcvtzs_v32f64_v32i32: ; CHECK-LABEL: fcvtzs_v32f64_v32i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl32 ; CHECK-NEXT: ptrue p0.d, vl32
; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzs z0.d, p1/m, z0.d
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d ; CHECK-NEXT: st1w { z0.d }, p0, [x1]
; CHECK-NEXT: ptrue p0.s, vl32
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: st1w { z0.s }, p0, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op1 = load <32 x double>, <32 x double>* %a %op1 = load <32 x double>, <32 x double>* %a
%res = fptosi <32 x double> %op1 to <32 x i32> %res = fptosi <32 x double> %op1 to <32 x i32>
store <32 x i32> %res, <32 x i32>* %b store <32 x i32> %res, <32 x i32>* %b
ret void ret void
} }
; ;
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