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llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
| Show First 20 Lines • Show All 2,901 Lines • ▼ Show 20 Lines | bool SelectionDAGLegalize::ExpandNode(SDNode *Node) { | ||||
| case ISD::FP_EXTEND: | case ISD::FP_EXTEND: | ||||
| if ((Tmp1 = EmitStackConvert(Node->getOperand(0), | if ((Tmp1 = EmitStackConvert(Node->getOperand(0), | ||||
| Node->getOperand(0).getValueType(), | Node->getOperand(0).getValueType(), | ||||
| Node->getValueType(0), dl))) | Node->getValueType(0), dl))) | ||||
| Results.push_back(Tmp1); | Results.push_back(Tmp1); | ||||
| break; | break; | ||||
| case ISD::BF16_TO_FP: { | case ISD::BF16_TO_FP: { | ||||
| // Always expand bf16 to f32 casts, they lower to ext + shift. | // Always expand bf16 to f32 casts, they lower to ext + shift. | ||||
| SDValue Op = DAG.getNode(ISD::BITCAST, dl, MVT::i16, Node->getOperand(0)); | SDValue Op = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Node->getOperand(0)); | ||||
| Op = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op); | |||||
| Op = DAG.getNode( | Op = DAG.getNode( | ||||
| ISD::SHL, dl, MVT::i32, Op, | ISD::SHL, dl, MVT::i32, Op, | ||||
| DAG.getConstant(16, dl, | DAG.getConstant(16, dl, | ||||
| TLI.getShiftAmountTy(MVT::i32, DAG.getDataLayout()))); | TLI.getShiftAmountTy(MVT::i32, DAG.getDataLayout()))); | ||||
| Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op); | Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op); | ||||
| Results.push_back(Op); | Results.push_back(Op); | ||||
| break; | break; | ||||
| } | } | ||||
| ▲ Show 20 Lines • Show All 2,196 Lines • Show Last 20 Lines | |||||