Page MenuHomePhabricator
Differential D122791 Diff 443540 llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll

Changeset View

Standalone View

View Options

llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64NOM
; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64M
define <vscale x 1 x i8> @vmul_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) { define <vscale x 1 x i8> @vmul_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
; CHECK-LABEL: vmul_vv_nxv1i8: ; CHECK-LABEL: vmul_vv_nxv1i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: vmul.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = mul <vscale x 1 x i8> %va, %vb %vc = mul <vscale x 1 x i8> %va, %vb
▲ Show 20 Lines • Show All 919 Lines • ▼ Show 20 Lines
; RV32-NEXT: vlse64.v v8, (a0), zero ; RV32-NEXT: vlse64.v v8, (a0), zero
; RV32-NEXT: sw a3, 12(sp) ; RV32-NEXT: sw a3, 12(sp)
; RV32-NEXT: sw a2, 8(sp) ; RV32-NEXT: sw a2, 8(sp)
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmul.vv v8, v8, v16 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmul_xx_nxv8i64: ; RV64NOM-LABEL: vmul_xx_nxv8i64:
; RV64: # %bb.0: ; RV64NOM: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; RV64NOM-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vmv.v.x v8, a0 ; RV64NOM-NEXT: vmv.v.x v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64NOM-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: ret ; RV64NOM-NEXT: ret
;
; RV64M-LABEL: vmul_xx_nxv8i64:
; RV64M: # %bb.0:
; RV64M-NEXT: mul a0, a0, a1
; RV64M-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64M-NEXT: vmv.v.x v8, a0
; RV64M-NEXT: ret
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0 %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = mul <vscale x 8 x i64> %splat1, %splat2 %v = mul <vscale x 8 x i64> %splat1, %splat2
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }