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lib/Target/Mips/AsmParser/MipsAsmParser.old.cpp
| Show First 20 Lines • Show All 230 Lines • ▼ Show 20 Lines | #include "MipsGenAsmMatcher.inc" | ||||
| bool expandDRotation(MCInst &Inst, SMLoc IDLoc, | bool expandDRotation(MCInst &Inst, SMLoc IDLoc, | ||||
| SmallVectorImpl<MCInst> &Instructions); | SmallVectorImpl<MCInst> &Instructions); | ||||
| bool expandDRotationImm(MCInst &Inst, SMLoc IDLoc, | bool expandDRotationImm(MCInst &Inst, SMLoc IDLoc, | ||||
| SmallVectorImpl<MCInst> &Instructions); | SmallVectorImpl<MCInst> &Instructions); | ||||
| bool expandAbs(MCInst &Inst, SMLoc IDLoc, | bool expandAbs(MCInst &Inst, SMLoc IDLoc, | ||||
| SmallVectorImpl<MCInst> &Instructions); | SmallVectorImpl<MCInst> &Instructions); | ||||
| bool expandMulImm(MCInst &Inst, SMLoc IDLoc, | |||||
| SmallVectorImpl<MCInst> &Instructions); | |||||
| //bool expandMulO(MCInst &Inst, SMLoc IDLoc, | |||||
| // SmallVectorImpl<MCInst> &Instructions); | |||||
| bool expandMulO_(MCInst &Inst, SMLoc IDLoc, | |||||
| SmallVectorImpl<MCInst> &Instructions); | |||||
| //bool expandMulOU(MCInst &Inst, SMLoc IDLoc, | |||||
| // SmallVectorImpl<MCInst> &Instructions); | |||||
| void createNop(bool hasShortDelaySlot, SMLoc IDLoc, | void createNop(bool hasShortDelaySlot, SMLoc IDLoc, | ||||
| SmallVectorImpl<MCInst> &Instructions); | SmallVectorImpl<MCInst> &Instructions); | ||||
| void createAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg, | void createAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg, | ||||
| bool Is64Bit, SmallVectorImpl<MCInst> &Instructions); | bool Is64Bit, SmallVectorImpl<MCInst> &Instructions); | ||||
| void createCpRestoreMemOp(bool IsLoad, int StackOffset, SMLoc IDLoc, | void createCpRestoreMemOp(bool IsLoad, int StackOffset, SMLoc IDLoc, | ||||
| SmallVectorImpl<MCInst> &Instructions); | SmallVectorImpl<MCInst> &Instructions); | ||||
| ▲ Show 20 Lines • Show All 1,841 Lines • ▼ Show 20 Lines | return expandDRotation(Inst, IDLoc, Instructions) ? MER_Fail | ||||
| : MER_Success; | : MER_Success; | ||||
| case Mips::DROLImm: | case Mips::DROLImm: | ||||
| case Mips::DRORImm: | case Mips::DRORImm: | ||||
| return expandDRotationImm(Inst, IDLoc, Instructions) ? MER_Fail | return expandDRotationImm(Inst, IDLoc, Instructions) ? MER_Fail | ||||
| : MER_Success; | : MER_Success; | ||||
| case Mips::ABSMacro: | case Mips::ABSMacro: | ||||
| return expandAbs(Inst, IDLoc, Instructions) ? MER_Fail | return expandAbs(Inst, IDLoc, Instructions) ? MER_Fail | ||||
| : MER_Success; | : MER_Success; | ||||
| case Mips::MULImm: | |||||
| case Mips::DMULImm: | |||||
| return expandMulImm(Inst, IDLoc, Instructions) ? MER_Fail | |||||
| : MER_Success; | |||||
| case Mips::MULO: | |||||
| case Mips::DMULO: | |||||
| //return expandMulO(Inst, IDLoc, Instructions) ? MER_Fail | |||||
| // : MER_Success; | |||||
| case Mips::MULOU: | |||||
| case Mips::DMULOU: | |||||
| //return expandMulOU(Inst, IDLoc, Instructions) ? MER_Fail | |||||
| // : MER_Success; | |||||
| return expandMulO_(Inst, IDLoc, Instructions) ? MER_Fail | |||||
| : MER_Success; | |||||
| } | } | ||||
| } | } | ||||
| bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, | bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, | ||||
| SmallVectorImpl<MCInst> &Instructions) { | SmallVectorImpl<MCInst> &Instructions) { | ||||
| // Create a JALR instruction which is going to replace the pseudo-JAL. | // Create a JALR instruction which is going to replace the pseudo-JAL. | ||||
| MCInst JalrInst; | MCInst JalrInst; | ||||
| JalrInst.setLoc(IDLoc); | JalrInst.setLoc(IDLoc); | ||||
| ▲ Show 20 Lines • Show All 1,444 Lines • ▼ Show 20 Lines | if (FirstRegOp != SecondRegOp) | ||||
| emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, Instructions); | emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, Instructions); | ||||
| else | else | ||||
| createNop(false, IDLoc, Instructions); | createNop(false, IDLoc, Instructions); | ||||
| emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, Instructions); | emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, Instructions); | ||||
| return false; | return false; | ||||
| } | } | ||||
| bool MipsAsmParser::expandMulImm(MCInst &Inst, SMLoc IDLoc, | |||||
| SmallVectorImpl<MCInst> &Instructions) { | |||||
| unsigned ATReg = Mips::NoRegister; | |||||
| unsigned DReg = Inst.getOperand(0).getReg(); | |||||
| unsigned SReg = Inst.getOperand(1).getReg(); | |||||
| int32_t ImmValue = Inst.getOperand(2).getImm(); | |||||
| ATReg = getATReg(Inst.getLoc()); | |||||
| if (!ATReg) | |||||
| return true; | |||||
| loadImmediate(ImmValue, ATReg, Mips::NoRegister, true, false, Inst.getLoc(), Instructions); | |||||
| if (Inst.getOpcode() == Mips::MULImm) | |||||
| emitRR(Mips::MULT, SReg, ATReg, IDLoc, Instructions); | |||||
| else | |||||
| emitRR(Mips::DMULT, SReg, ATReg, IDLoc, Instructions); | |||||
| emitR(Mips::MFLO, DReg, IDLoc, Instructions); | |||||
| return false; | |||||
| } | |||||
| //bool MipsAsmParser::expandMulO(MCInst &Inst, SMLoc IDLoc, | |||||
| // SmallVectorImpl<MCInst> &Instructions) { | |||||
| // unsigned ATReg = Mips::NoRegister; | |||||
| // unsigned DReg = Inst.getOperand(0).getReg(); | |||||
| // unsigned SReg = Inst.getOperand(1).getReg(); | |||||
| // unsigned TReg = Inst.getOperand(2).getReg(); | |||||
| // | |||||
| // ATReg = getATReg(Inst.getLoc()); | |||||
| // if (!ATReg) | |||||
| // return true; | |||||
| // | |||||
| // if (Inst.getOpcode() == Mips::MULO) | |||||
| // emitRR(Mips::MULT, SReg, TReg, IDLoc, Instructions); | |||||
| // else | |||||
| // emitRR(Mips::DMULT, SReg, TReg, IDLoc, Instructions); | |||||
| // emitR(Mips::MFLO, DReg, IDLoc, Instructions); | |||||
| // if (Inst.getOpcode() == Mips::MULO) | |||||
| // emitRRI(Mips::SRA, DReg, DReg, 0x1F, IDLoc, Instructions); | |||||
| // else | |||||
| // emitRRI(Mips::DSRA32, DReg, DReg, 0x1F, IDLoc, Instructions); | |||||
| // emitR(Mips::MFHI, ATReg, IDLoc, Instructions); | |||||
| // emitRRI(Mips::BEQ, DReg, ATReg, 8, IDLoc, Instructions); | |||||
| // if (AssemblerOptions.back()->isReorder()) | |||||
| // createNop(false, IDLoc, Instructions); | |||||
| // emitII(Mips::BREAK,6, 0, IDLoc, Instructions); | |||||
| // emitR(Mips::MFLO, DReg, IDLoc, Instructions); | |||||
| // | |||||
| // return false; | |||||
| //} | |||||
| bool MipsAsmParser::expandMulO_(MCInst &Inst, SMLoc IDLoc, | |||||
| SmallVectorImpl<MCInst> &Instructions) { | |||||
| unsigned ATReg = Mips::NoRegister; | |||||
| unsigned DReg = Inst.getOperand(0).getReg(); | |||||
| unsigned SReg = Inst.getOperand(1).getReg(); | |||||
| unsigned TReg = Inst.getOperand(2).getReg(); | |||||
| ATReg = getATReg(Inst.getLoc()); | |||||
| if (!ATReg) | |||||
| return true; | |||||
| switch (Inst.getOpcode()) { | |||||
| default: | |||||
| llvm_unreachable("unexpected instruction opcode"); | |||||
| case Mips::MULO: | |||||
| emitRR(Mips::MULT, SReg, TReg, IDLoc, Instructions); | |||||
| break; | |||||
| case Mips::MULOU: | |||||
| emitRR(Mips::MULTu, SReg, TReg, IDLoc, Instructions); | |||||
| emitR(Mips::MFHI, ATReg, IDLoc, Instructions); | |||||
| break; | |||||
| case Mips::DMULO: | |||||
| emitRR(Mips::DMULT, SReg, TReg, IDLoc, Instructions); | |||||
| break; | |||||
| case Mips::DMULOU: | |||||
| emitRR(Mips::DMULTu, SReg, TReg, IDLoc, Instructions); | |||||
| emitR(Mips::MFHI, ATReg, IDLoc, Instructions); | |||||
| break; | |||||
| } | |||||
| emitR(Mips::MFLO, DReg, IDLoc, Instructions); | |||||
| switch (Inst.getOpcode()) { | |||||
| default: | |||||
| llvm_unreachable("unexpected instruction opcode"); | |||||
| case Mips::MULO: | |||||
| emitRRI(Mips::SRA, DReg, DReg, 0x1F, IDLoc, Instructions); | |||||
| emitR(Mips::MFHI, ATReg, IDLoc, Instructions); | |||||
| emitRRI(Mips::BEQ, DReg, ATReg, 8, IDLoc, Instructions); | |||||
| break; | |||||
| case Mips::MULOU: | |||||
| emitRRI(Mips::BEQ, ATReg, Mips::ZERO, 8, IDLoc, Instructions); | |||||
| break; | |||||
| case Mips::DMULO: | |||||
| emitRRI(Mips::DSRA32, DReg, DReg, 0x1F, IDLoc, Instructions); | |||||
| emitR(Mips::MFHI, ATReg, IDLoc, Instructions); | |||||
| emitRRI(Mips::BEQ, DReg, ATReg, 8, IDLoc, Instructions); | |||||
| break; | |||||
| case Mips::DMULOU: | |||||
| emitRRI(Mips::BEQ, ATReg, Mips::ZERO, 8, IDLoc, Instructions); | |||||
| break; | |||||
| } | |||||
| if (AssemblerOptions.back()->isReorder()) | |||||
| createNop(false, IDLoc, Instructions); | |||||
| emitII(Mips::BREAK,6, 0, IDLoc, Instructions); | |||||
| emitR(Mips::MFLO, DReg, IDLoc, Instructions); | |||||
| return false; | |||||
| } | |||||
| //bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc, | |||||
| // SmallVectorImpl<MCInst> &Instructions) { | |||||
| // unsigned ATReg = Mips::NoRegister; | |||||
| // unsigned DReg = Inst.getOperand(0).getReg(); | |||||
| // unsigned SReg = Inst.getOperand(1).getReg(); | |||||
| // unsigned TReg = Inst.getOperand(2).getReg(); | |||||
| // | |||||
| // ATReg = getATReg(Inst.getLoc()); | |||||
| // if (!ATReg) | |||||
| // return true; | |||||
| // | |||||
| // if (Inst.getOpcode() == Mips::MULOU) | |||||
| // emitRR(Mips::MULTu, SReg, TReg, IDLoc, Instructions); | |||||
| // else | |||||
| // emitRR(Mips::DMULTu, SReg, TReg, IDLoc, Instructions); | |||||
| // emitR(Mips::MFHI, ATReg, IDLoc, Instructions); | |||||
| // emitR(Mips::MFLO, DReg, IDLoc, Instructions); | |||||
| // emitRRI(Mips::BEQ, ATReg, Mips::ZERO, 8, IDLoc, Instructions); | |||||
| // if (AssemblerOptions.back()->isReorder()) | |||||
| // createNop(false, IDLoc, Instructions); | |||||
| // emitII(Mips::BREAK, 6, 0, IDLoc, Instructions); | |||||
| // | |||||
| // return false; | |||||
| //} | |||||
| void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc, | void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc, | ||||
| SmallVectorImpl<MCInst> &Instructions) { | SmallVectorImpl<MCInst> &Instructions) { | ||||
| if (hasShortDelaySlot) | if (hasShortDelaySlot) | ||||
| emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, Instructions); | emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, Instructions); | ||||
| else | else | ||||
| emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, Instructions); | emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, Instructions); | ||||
| } | } | ||||
| ▲ Show 20 Lines • Show All 2,673 Lines • Show Last 20 Lines | |||||