Differential D128681 Diff 441432 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp

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llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp

Show First 20 Lines • Show All 434 Lines • ▼ Show 20 Lines	if (N->getOpcode() == ISD::CopyFromReg) {
}		}
}		}
return N->getSimpleValueType(NumRes);		return N->getSimpleValueType(NumRes);
}		}

/// CheckForLiveRegDef - Return true and update live register vector if the		/// CheckForLiveRegDef - Return true and update live register vector if the
/// specified register def of the specified SUnit clobbers any "live" registers.		/// specified register def of the specified SUnit clobbers any "live" registers.
static bool CheckForLiveRegDef(SUnit *SU, unsigned Reg,		static bool CheckForLiveRegDef(SUnit *SU, unsigned Reg,
std::vector<SUnit*> &LiveRegDefs,		std::vector<SUnit *> &LiveRegDefs,
SmallSet<unsigned, 4> &RegAdded,		SmallSet<unsigned, 4> &RegAdded,
SmallVectorImpl<unsigned> &LRegs,		SmallVectorImpl<unsigned> &LRegs,
const TargetRegisterInfo *TRI) {		const TargetRegisterInfo *TRI,
		const SDNode *Node = nullptr) {
bool Added = false;		bool Added = false;
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {		for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
if (LiveRegDefs[AI] && LiveRegDefs[AI] != SU) {		// Check if Ref is live.
		if (!LiveRegDefs[*AI])
		rampitecUnsubmitted Not Done Reply Inline Actions The check for LiveRegDefs[AI] is excessive. If Node is not null the last check will not succeed. rampitec:* The check for LiveRegDefs[*AI] is excessive. If Node is not null the last check will not…
		continue;

		// Allow multiple uses of the same def.
		if (LiveRegDefs[*AI] == SU)
		continue;

		// Allow multiple uses of same def
		if (Node && LiveRegDefs[*AI]->getNode() == Node)
		continue;

		// Add Reg to the set of interfering live regs.
if (RegAdded.insert(*AI).second) {		if (RegAdded.insert(*AI).second) {
LRegs.push_back(*AI);		LRegs.push_back(*AI);
Added = true;		Added = true;
}		}
}		}
}
return Added;		return Added;
}		}

/// DelayForLiveRegsBottomUp - Returns true if it is necessary to delay		/// DelayForLiveRegsBottomUp - Returns true if it is necessary to delay
/// scheduling of the given node to satisfy live physical register dependencies.		/// scheduling of the given node to satisfy live physical register dependencies.
/// If the specific node is the last one that's available to schedule, do		/// If the specific node is the last one that's available to schedule, do
/// whatever is necessary (i.e. backtracking or cloning) to make it possible.		/// whatever is necessary (i.e. backtracking or cloning) to make it possible.
bool ScheduleDAGFast::DelayForLiveRegsBottomUp(SUnit *SU,		bool ScheduleDAGFast::DelayForLiveRegsBottomUp(SUnit *SU,
Show All 33 Lines	if (Node->getOpcode() == ISD::INLINEASM \|\|
if (Register::isPhysicalRegister(Reg))		if (Register::isPhysicalRegister(Reg))
CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI);		CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI);
}		}
} else		} else
i += NumVals;		i += NumVals;
}		}
continue;		continue;
}		}

		if (Node->getOpcode() == ISD::CopyToReg) {
		Register Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
		if (Reg.isPhysical()) {
		SDNode *SrcNode = Node->getOperand(2).getNode();
		CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI, SrcNode);
		}
		}

if (!Node->isMachineOpcode())		if (!Node->isMachineOpcode())
continue;		continue;
const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());		const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
if (!MCID.ImplicitDefs)		if (!MCID.ImplicitDefs)
continue;		continue;
for (const MCPhysReg Reg = MCID.getImplicitDefs(); Reg; ++Reg) {		for (const MCPhysReg Reg = MCID.getImplicitDefs(); Reg; ++Reg) {
CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);		CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
}		}
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