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Differential D128898 Diff 441318 llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

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llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

Show All 40 LinesLoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, GRLenVT, setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, GRLenVT,
MVT::i1, Promote); MVT::i1, Promote);
// TODO: add necessary setOperationAction calls later. // TODO: add necessary setOperationAction calls later.
setOperationAction(ISD::SHL_PARTS, GRLenVT, Custom); setOperationAction(ISD::SHL_PARTS, GRLenVT, Custom);
setOperationAction(ISD::SRA_PARTS, GRLenVT, Custom); setOperationAction(ISD::SRA_PARTS, GRLenVT, Custom);
setOperationAction(ISD::SRL_PARTS, GRLenVT, Custom); setOperationAction(ISD::SRL_PARTS, GRLenVT, Custom);
setOperationAction(ISD::GlobalAddress, GRLenVT, Custom); setOperationAction({ISD::GlobalAddress, ISD::ConstantPool}, GRLenVT, Custom);
if (Subtarget.is64Bit()) { if (Subtarget.is64Bit()) {
setOperationAction(ISD::SHL, MVT::i32, Custom); setOperationAction(ISD::SHL, MVT::i32, Custom);
setOperationAction(ISD::SRA, MVT::i32, Custom); setOperationAction(ISD::SRA, MVT::i32, Custom);
setOperationAction(ISD::SRL, MVT::i32, Custom); setOperationAction(ISD::SRL, MVT::i32, Custom);
} }
static const ISD::CondCode FPCCToExpand[] = {ISD::SETOGT, ISD::SETOGE, static const ISD::CondCode FPCCToExpand[] = {ISD::SETOGT, ISD::SETOGE,
ISD::SETUGT, ISD::SETUGE}; ISD::SETUGT, ISD::SETUGE};
if (Subtarget.hasBasicF()) { if (Subtarget.hasBasicF()) {
setCondCodeAction(FPCCToExpand, MVT::f32, Expand); setCondCodeAction(FPCCToExpand, MVT::f32, Expand);
setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
} }
if (Subtarget.hasBasicD()) { if (Subtarget.hasBasicD()) {
setCondCodeAction(FPCCToExpand, MVT::f64, Expand); setCondCodeAction(FPCCToExpand, MVT::f64, Expand);
setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
} }
setOperationAction(ISD::BR_CC, GRLenVT, Expand); setOperationAction(ISD::BR_CC, GRLenVT, Expand);
setOperationAction(ISD::SELECT_CC, GRLenVT, Expand); setOperationAction(ISD::SELECT_CC, GRLenVT, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
// Compute derived properties from the register classes. // Compute derived properties from the register classes.
computeRegisterProperties(STI.getRegisterInfo()); computeRegisterProperties(STI.getRegisterInfo());
Show All 25 Lines case ISD::SRL_PARTS:
return lowerShiftRightParts(Op, DAG, false); return lowerShiftRightParts(Op, DAG, false);
case ISD::SHL: case ISD::SHL:
case ISD::SRA: case ISD::SRA:
case ISD::SRL: case ISD::SRL:
// This can be called for an i32 shift amount that needs to be promoted. // This can be called for an i32 shift amount that needs to be promoted.
assert(Op.getOperand(1).getValueType() == MVT::i32 && Subtarget.is64Bit() && assert(Op.getOperand(1).getValueType() == MVT::i32 && Subtarget.is64Bit() &&
"Unexpected custom legalisation"); "Unexpected custom legalisation");
return SDValue(); return SDValue();
case ISD::ConstantPool:
return lowerConstantPool(Op, DAG);
} }
} }
SDValue LoongArchTargetLowering::lowerConstantPool(SDValue Op,
SelectionDAG &DAG) const {
SDLoc DL(Op);
EVT Ty = Op.getValueType();
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
// FIXME: Only support PC-relative addressing to access the symbol.
// Target flags will added later.
xen0nUnsubmitted
Not Done
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nit: "will be added later"

xen0n: nit: "will be added later"
gonglingqinAuthorUnsubmitted
Done
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Thanks. I will change that.

gonglingqin: Thanks. I will change that.
if (!isPositionIndependent()) {
SDValue ConstantN = DAG.getTargetConstantPool(
N->getConstVal(), Ty, N->getAlign(), N->getOffset());
SDValue AddrHi(DAG.getMachineNode(LoongArch::PCALAU12I, DL, Ty, ConstantN),
0);
SDValue Addr(DAG.getMachineNode(Subtarget.is64Bit() ? LoongArch::ADDI_D
: LoongArch::ADDI_W,
DL, Ty, AddrHi, ConstantN),
0);
return Addr;
}
report_fatal_error("Unable to lower ConstantPool");
}
SDValue LoongArchTargetLowering::lowerGlobalAddress(SDValue Op, SDValue LoongArchTargetLowering::lowerGlobalAddress(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
SDLoc DL(Op); SDLoc DL(Op);
EVT Ty = getPointerTy(DAG.getDataLayout()); EVT Ty = getPointerTy(DAG.getDataLayout());
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
unsigned ADDIOp = Subtarget.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W; unsigned ADDIOp = Subtarget.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
// FIXME: Only support PC-relative addressing to access the symbol. // FIXME: Only support PC-relative addressing to access the symbol.
▲ Show 20 Lines • Show All 559 Lines • ▼ Show 20 LinesSDValue LoongArchTargetLowering::LowerReturn(
RetOps[0] = Chain; // Update chain. RetOps[0] = Chain; // Update chain.
// Add the glue node if we have it. // Add the glue node if we have it.
if (Glue.getNode()) if (Glue.getNode())
RetOps.push_back(Glue); RetOps.push_back(Glue);
return DAG.getNode(LoongArchISD::RET, DL, MVT::Other, RetOps); return DAG.getNode(LoongArchISD::RET, DL, MVT::Other, RetOps);
} }
bool LoongArchTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
bool ForCodeSize) const {
assert((VT == MVT::f32 || VT == MVT::f64) && "Unexpected VT");
if (VT == MVT::f32 && !Subtarget.hasBasicF())
return false;
if (VT == MVT::f64 && !Subtarget.hasBasicD())
return false;
return (Imm.isZero() || Imm.isExactlyValue(+1.0));
}