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Differential D128604 Diff 441052 llvm/lib/Target/RISCV/RISCVISelLowering.cpp

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llvm/lib/Target/RISCV/RISCVISelLowering.cpp

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Show First 20 Lines • Show All 277 Lines • ▼ Show 20 Lines if (Subtarget.is64Bit())
{ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, {ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF},
MVT::i32, Custom); MVT::i32, Custom);
} else { } else {
setOperationAction({ISD::CTTZ, ISD::CTLZ, ISD::CTPOP}, XLenVT, Expand); setOperationAction({ISD::CTTZ, ISD::CTLZ, ISD::CTPOP}, XLenVT, Expand);
if (Subtarget.is64Bit()) if (Subtarget.is64Bit())
setOperationAction(ISD::ABS, MVT::i32, Custom); setOperationAction(ISD::ABS, MVT::i32, Custom);
} }
if (Subtarget.hasStdExtZbpbo()) {
setOperationAction({ISD::SMIN, ISD::SMAX}, XLenVT, Legal);
setOperationAction(ISD::CTLZ, MVT::i32, Legal);
setOperationAction({ISD::BITREVERSE, ISD::BSWAP}, MVT::i16, Custom);
}
if (Subtarget.hasStdExtZbt()) { if (Subtarget.hasStdExtZbt()) {
setOperationAction({ISD::FSHL, ISD::FSHR}, XLenVT, Custom); setOperationAction({ISD::FSHL, ISD::FSHR}, XLenVT, Custom);
setOperationAction(ISD::SELECT, XLenVT, Legal); setOperationAction(ISD::SELECT, XLenVT, Legal);
if (Subtarget.is64Bit()) if (Subtarget.is64Bit())
setOperationAction({ISD::FSHL, ISD::FSHR}, MVT::i32, Custom); setOperationAction({ISD::FSHL, ISD::FSHR}, MVT::i32, Custom);
} else { } else {
▲ Show 20 Lines • Show All 6,791 Lines • ▼ Show 20 Lines case RISCVISD::SHFL: {
break; break;
} }
case ISD::BSWAP: case ISD::BSWAP:
case ISD::BITREVERSE: { case ISD::BITREVERSE: {
MVT VT = N->getSimpleValueType(0); MVT VT = N->getSimpleValueType(0);
MVT XLenVT = Subtarget.getXLenVT(); MVT XLenVT = Subtarget.getXLenVT();
assert((VT == MVT::i8 || VT == MVT::i16 || assert((VT == MVT::i8 || VT == MVT::i16 ||
(VT == MVT::i32 && Subtarget.is64Bit())) && (VT == MVT::i32 && Subtarget.is64Bit())) &&
Subtarget.hasStdExtZbp() && "Unexpected custom legalisation"); (Subtarget.hasStdExtZbp() || Subtarget.hasStdExtZbpbo()) &&
"Unexpected custom legalisation");
SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, N->getOperand(0)); SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, N->getOperand(0));
unsigned Imm = VT.getSizeInBits() - 1; unsigned Imm = VT.getSizeInBits() - 1;
// If this is BSWAP rather than BITREVERSE, clear the lower 3 bits. // If this is BSWAP rather than BITREVERSE, clear the lower 3 bits.
if (N->getOpcode() == ISD::BSWAP) if (N->getOpcode() == ISD::BSWAP)
Imm &= ~0x7U; Imm &= ~0x7U;
SDValue GREVI = DAG.getNode(RISCVISD::GREV, DL, XLenVT, NewOp0, SDValue GREVI = DAG.getNode(RISCVISD::GREV, DL, XLenVT, NewOp0,
DAG.getConstant(Imm, DL, XLenVT)); DAG.getConstant(Imm, DL, XLenVT));
// ReplaceNodeResults requires we maintain the same type for the return // ReplaceNodeResults requires we maintain the same type for the return
▲ Show 20 Lines • Show All 688 Lines • ▼ Show 20 Lines bool IsWInstruction =
N->getOpcode() == RISCVISD::RORW || N->getOpcode() == RISCVISD::ROLW; N->getOpcode() == RISCVISD::RORW || N->getOpcode() == RISCVISD::ROLW;
assert((N->getOpcode() == ISD::ROTR || N->getOpcode() == ISD::ROTL || assert((N->getOpcode() == ISD::ROTR || N->getOpcode() == ISD::ROTL ||
IsWInstruction) && IsWInstruction) &&
"Unexpected opcode!"); "Unexpected opcode!");
SDValue Src = N->getOperand(0); SDValue Src = N->getOperand(0);
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
SDLoc DL(N); SDLoc DL(N);
if (!Subtarget.hasStdExtZbp() || Src.getOpcode() != RISCVISD::GREV) if (!(Subtarget.hasStdExtZbp() || Subtarget.hasStdExtZbpbo()) ||
Src.getOpcode() != RISCVISD::GREV)
return SDValue(); return SDValue();
if (!isa<ConstantSDNode>(N->getOperand(1)) || if (!isa<ConstantSDNode>(N->getOperand(1)) ||
!isa<ConstantSDNode>(Src.getOperand(1))) !isa<ConstantSDNode>(Src.getOperand(1)))
return SDValue(); return SDValue();
unsigned BitWidth = IsWInstruction ? 32 : VT.getSizeInBits(); unsigned BitWidth = IsWInstruction ? 32 : VT.getSizeInBits();
assert(isPowerOf2_32(BitWidth) && "Expected a power of 2"); assert(isPowerOf2_32(BitWidth) && "Expected a power of 2");
▲ Show 20 Lines • Show All 4,523 Lines • Show Last 20 Lines