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clang/test/CodeGen/RISCV/rvp-intrinsics/riscv64-zbpbo.c
- This file was added.
| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py | |||||
| // RUN: %clang_cc1 -no-opaque-pointers -triple riscv64 -target-feature +experimental-zbpbo -emit-llvm %s -o - \ | |||||
| // RUN: | FileCheck %s -check-prefix=RV64ZBPBO | |||||
| // RV64ZBPBO-LABEL: @fsrw( | |||||
| // RV64ZBPBO-NEXT: entry: | |||||
| // RV64ZBPBO-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8 | |||||
| // RV64ZBPBO-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8 | |||||
| // RV64ZBPBO-NEXT: [[RS3_ADDR:%.*]] = alloca i64, align 8 | |||||
| // RV64ZBPBO-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8 | |||||
| // RV64ZBPBO-NEXT: store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8 | |||||
| // RV64ZBPBO-NEXT: store i64 [[RS3:%.*]], i64* [[RS3_ADDR]], align 8 | |||||
| // RV64ZBPBO-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8 | |||||
| // RV64ZBPBO-NEXT: [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8 | |||||
| // RV64ZBPBO-NEXT: [[TMP2:%.*]] = load i64, i64* [[RS3_ADDR]], align 8 | |||||
| // RV64ZBPBO-NEXT: [[TMP3:%.*]] = call i64 @llvm.riscv.fsr.i64(i64 [[TMP0]], i64 [[TMP1]], i64 [[TMP2]]) | |||||
| // RV64ZBPBO-NEXT: ret i64 [[TMP3]] | |||||
| // | |||||
| long fsrw(long rs1, long rs2, long rs3) { | |||||
| return __builtin_riscv_fsr_64(rs1, rs2, rs3); | |||||
| } | |||||
| // RV64ZBPBO-LABEL: @grevi( | |||||
| // RV64ZBPBO-NEXT: entry: | |||||
| // RV64ZBPBO-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8 | |||||
| // RV64ZBPBO-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8 | |||||
| // RV64ZBPBO-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8 | |||||
| // RV64ZBPBO-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.grev.i64(i64 [[TMP0]], i64 13) | |||||
| // RV64ZBPBO-NEXT: ret i64 [[TMP1]] | |||||
| // | |||||
| long grevi(long rs1) { | |||||
| return __builtin_riscv_grev_64(rs1, 13); | |||||
| } | |||||