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clang/test/CodeGen/RISCV/rvp-intrinsics/riscv32-zbpbo.c
- This file was added.
| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py | |||||
| // RUN: %clang_cc1 -no-opaque-pointers -triple riscv32 -target-feature +experimental-zbpbo -emit-llvm %s -o - \ | |||||
| // RUN: | FileCheck %s -check-prefix=RV32ZBPBO | |||||
| // RV32ZBPBO-LABEL: @clz_32( | |||||
| // RV32ZBPBO-NEXT: entry: | |||||
| // RV32ZBPBO-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 | |||||
| // RV32ZBPBO-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 | |||||
| // RV32ZBPBO-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 | |||||
| // RV32ZBPBO-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false) | |||||
| // RV32ZBPBO-NEXT: ret i32 [[TMP1]] | |||||
| // | |||||
| int clz_32(int a) { | |||||
| return __builtin_riscv_clz_32(a); | |||||
| } | |||||
| // RV32ZBPBO-LABEL: @fsr( | |||||
| // RV32ZBPBO-NEXT: entry: | |||||
| // RV32ZBPBO-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 | |||||
| // RV32ZBPBO-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4 | |||||
| // RV32ZBPBO-NEXT: [[RS3_ADDR:%.*]] = alloca i32, align 4 | |||||
| // RV32ZBPBO-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4 | |||||
| // RV32ZBPBO-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4 | |||||
| // RV32ZBPBO-NEXT: store i32 [[RS3:%.*]], i32* [[RS3_ADDR]], align 4 | |||||
| // RV32ZBPBO-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4 | |||||
| // RV32ZBPBO-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4 | |||||
| // RV32ZBPBO-NEXT: [[TMP2:%.*]] = load i32, i32* [[RS3_ADDR]], align 4 | |||||
| // RV32ZBPBO-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.fsr.i32(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) | |||||
| // RV32ZBPBO-NEXT: ret i32 [[TMP3]] | |||||
| // | |||||
| int fsr(int rs1, int rs2, int rs3) { | |||||
| return __builtin_riscv_fsr_32(rs1, rs2, rs3); | |||||
| } | |||||
| // RV32ZBPBO-LABEL: @fsri( | |||||
| // RV32ZBPBO-NEXT: entry: | |||||
| // RV32ZBPBO-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 | |||||
| // RV32ZBPBO-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4 | |||||
| // RV32ZBPBO-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4 | |||||
| // RV32ZBPBO-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4 | |||||
| // RV32ZBPBO-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4 | |||||
| // RV32ZBPBO-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4 | |||||
| // RV32ZBPBO-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.fsr.i32(i32 [[TMP0]], i32 [[TMP1]], i32 15) | |||||
| // RV32ZBPBO-NEXT: ret i32 [[TMP2]] | |||||
| // | |||||
| int fsri(int rs1, int rs2) { | |||||
| return __builtin_riscv_fsr_32(rs1, rs2, 15); | |||||
| } | |||||
| // RV32ZBPBO-LABEL: @grevi( | |||||
| // RV32ZBPBO-NEXT: entry: | |||||
| // RV32ZBPBO-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 | |||||
| // RV32ZBPBO-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4 | |||||
| // RV32ZBPBO-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4 | |||||
| // RV32ZBPBO-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.grev.i32(i32 [[TMP0]], i32 13) | |||||
| // RV32ZBPBO-NEXT: ret i32 [[TMP1]] | |||||
| // | |||||
| long grevi(long rs1) { | |||||
| return __builtin_riscv_grev_32(rs1, 13); | |||||
| } | |||||