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llvm/test/CodeGen/RISCV/rv32zbpbo-intrinsics.ll
- This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py | |||||
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbpbo -verify-machineinstrs < %s \ | |||||
; RUN: | FileCheck %s -check-prefix=RV32ZBPBO | |||||
declare i32 @llvm.riscv.fsr.i32(i32, i32, i32) | |||||
define i32 @fsr_i32(i32 %a, i32 %b, i32 %c) nounwind { | |||||
; RV32ZBPBO-LABEL: fsr_i32: | |||||
; RV32ZBPBO: # %bb.0: | |||||
; RV32ZBPBO-NEXT: fsr a0, a0, a1, a2 | |||||
; RV32ZBPBO-NEXT: ret | |||||
%1 = call i32 @llvm.riscv.fsr.i32(i32 %a, i32 %b, i32 %c) | |||||
ret i32 %1 | |||||
} | |||||
define i32 @fsri_i32(i32 %a, i32 %b) nounwind { | |||||
; RV32ZBPBO-LABEL: fsri_i32: | |||||
; RV32ZBPBO: # %bb.0: | |||||
; RV32ZBPBO-NEXT: fsri a0, a0, a1, 15 | |||||
; RV32ZBPBO-NEXT: ret | |||||
%1 = call i32 @llvm.riscv.fsr.i32(i32 %a, i32 %b, i32 15) | |||||
ret i32 %1 | |||||
} | |||||
declare i32 @llvm.riscv.grev.i32(i32 %a, i32 %b) | |||||
define i32 @revi32(i32 %a) nounwind { | |||||
; RV32ZBPBO-LABEL: revi32: | |||||
; RV32ZBPBO: # %bb.0: | |||||
; RV32ZBPBO-NEXT: rev a0, a0 | |||||
; RV32ZBPBO-NEXT: ret | |||||
%tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 31) | |||||
ret i32 %tmp | |||||
} |