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llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
| Show First 20 Lines • Show All 396 Lines • ▼ Show 20 Lines | def BEXTI : RVBShift_ri<0b01001, 0b101, OPC_OP_IMM, "bexti">, | ||||
| Sched<[WriteSingleBitImm, ReadSingleBitImm]>; | Sched<[WriteSingleBitImm, ReadSingleBitImm]>; | ||||
| } // Predicates = [HasStdExtZbs] | } // Predicates = [HasStdExtZbs] | ||||
| let Predicates = [HasStdExtZbp] in { | let Predicates = [HasStdExtZbp] in { | ||||
| def GORC : ALU_rr<0b0010100, 0b101, "gorc">, | def GORC : ALU_rr<0b0010100, 0b101, "gorc">, | ||||
| Sched<[WriteORC, ReadORC, ReadORC]>; | Sched<[WriteORC, ReadORC, ReadORC]>; | ||||
| def GREV : ALU_rr<0b0110100, 0b101, "grev">, | def GREV : ALU_rr<0b0110100, 0b101, "grev">, | ||||
| Sched<[WriteREV, ReadREV, ReadREV]>; | Sched<[WriteREV, ReadREV, ReadREV]>; | ||||
| } // Predicates = [HasStdExtZbp] | |||||
| let Predicates = [HasStdExtZbpOrZbpbo] in | |||||
| def GREVI : RVBShift_ri<0b01101, 0b101, OPC_OP_IMM, "grevi">, | def GREVI : RVBShift_ri<0b01101, 0b101, OPC_OP_IMM, "grevi">, | ||||
| Sched<[WriteREVImm, ReadREVImm]>; | Sched<[WriteREVImm, ReadREVImm]>; | ||||
| let Predicates = [HasStdExtZbp] in { | |||||
| def GORCI : RVBShift_ri<0b00101, 0b101, OPC_OP_IMM, "gorci">, | def GORCI : RVBShift_ri<0b00101, 0b101, OPC_OP_IMM, "gorci">, | ||||
| Sched<[WriteORCImm, ReadORCImm]>; | Sched<[WriteORCImm, ReadORCImm]>; | ||||
| def SHFL : ALU_rr<0b0000100, 0b001, "shfl">, | def SHFL : ALU_rr<0b0000100, 0b001, "shfl">, | ||||
| Sched<[WriteSHFL, ReadSHFL, ReadSHFL]>; | Sched<[WriteSHFL, ReadSHFL, ReadSHFL]>; | ||||
| def UNSHFL : ALU_rr<0b0000100, 0b101, "unshfl">, | def UNSHFL : ALU_rr<0b0000100, 0b101, "unshfl">, | ||||
| Sched<[WriteUNSHFL, ReadUNSHFL, ReadUNSHFL]>; | Sched<[WriteUNSHFL, ReadUNSHFL, ReadUNSHFL]>; | ||||
| Show All 30 Lines | |||||
| // the draft bit manipulation specification they were included in. However, we | // the draft bit manipulation specification they were included in. However, we | ||||
| // use the mnemonics given to them in the ratified Zbkx extension. | // use the mnemonics given to them in the ratified Zbkx extension. | ||||
| let Predicates = [HasStdExtZbpOrZbkx] in { | let Predicates = [HasStdExtZbpOrZbkx] in { | ||||
| def XPERM4 : ALU_rr<0b0010100, 0b010, "xperm4">, Sched<[]>; | def XPERM4 : ALU_rr<0b0010100, 0b010, "xperm4">, Sched<[]>; | ||||
| def XPERM8 : ALU_rr<0b0010100, 0b100, "xperm8">, Sched<[]>; | def XPERM8 : ALU_rr<0b0010100, 0b100, "xperm8">, Sched<[]>; | ||||
| } // Predicates = [HasStdExtZbpOrZbkx] | } // Predicates = [HasStdExtZbpOrZbkx] | ||||
| let Predicates = [HasStdExtZbt] in { | let Predicates = [HasStdExtZbt] in { | ||||
| def CMIX : RVBTernaryR<0b11, 0b001, OPC_OP, "cmix", "$rd, $rs2, $rs1, $rs3">, | |||||
| Sched<[WriteCMix, ReadCMix, ReadCMix, ReadCMix]>; | |||||
| def CMOV : RVBTernaryR<0b11, 0b101, OPC_OP, "cmov", "$rd, $rs2, $rs1, $rs3">, | def CMOV : RVBTernaryR<0b11, 0b101, OPC_OP, "cmov", "$rd, $rs2, $rs1, $rs3">, | ||||
| Sched<[WriteCMov, ReadCMov, ReadCMov, ReadCMov]>; | Sched<[WriteCMov, ReadCMov, ReadCMov, ReadCMov]>; | ||||
| def FSL : RVBTernaryR<0b10, 0b001, OPC_OP, "fsl", "$rd, $rs1, $rs3, $rs2">, | def FSL : RVBTernaryR<0b10, 0b001, OPC_OP, "fsl", "$rd, $rs1, $rs3, $rs2">, | ||||
| Sched<[WriteFSReg, ReadFSReg, ReadFSReg, ReadFSReg]>; | Sched<[WriteFSReg, ReadFSReg, ReadFSReg, ReadFSReg]>; | ||||
| } // Predicates = [HasStdExtZbt] | |||||
| let Predicates = [HasStdExtZbtOrZbpbo] in { | |||||
| def CMIX : RVBTernaryR<0b11, 0b001, OPC_OP, "cmix", "$rd, $rs2, $rs1, $rs3">, | |||||
| Sched<[WriteCMix, ReadCMix, ReadCMix, ReadCMix]>; | |||||
| def FSR : RVBTernaryR<0b10, 0b101, OPC_OP, "fsr", "$rd, $rs1, $rs3, $rs2">, | def FSR : RVBTernaryR<0b10, 0b101, OPC_OP, "fsr", "$rd, $rs1, $rs3, $rs2">, | ||||
Jim: FSR and FSRI only exist on RV32 for Zbpbo. | |||||
| Sched<[WriteFSReg, ReadFSReg, ReadFSReg, ReadFSReg]>; | Sched<[WriteFSReg, ReadFSReg, ReadFSReg, ReadFSReg]>; | ||||
| def FSRI : RVBTernaryImm6<0b101, OPC_OP_IMM, "fsri", | def FSRI : RVBTernaryImm6<0b101, OPC_OP_IMM, "fsri", | ||||
| "$rd, $rs1, $rs3, $shamt">, | "$rd, $rs1, $rs3, $shamt">, | ||||
| Sched<[WriteFSRImm, ReadFSRImm, ReadFSRImm]>; | Sched<[WriteFSRImm, ReadFSRImm, ReadFSRImm]>; | ||||
| } // Predicates = [HasStdExtZbt] | } // Predicates = [HasStdExtZbtOrZbpbo] | ||||
| let Predicates = [HasStdExtZbt, IsRV64] in { | let Predicates = [HasStdExtZbt, IsRV64] in { | ||||
| def FSLW : RVBTernaryR<0b10, 0b001, OPC_OP_32, | def FSLW : RVBTernaryR<0b10, 0b001, OPC_OP_32, | ||||
| "fslw", "$rd, $rs1, $rs3, $rs2">, | "fslw", "$rd, $rs1, $rs3, $rs2">, | ||||
| Sched<[WriteFSReg32, ReadFSReg32, ReadFSReg32, ReadFSReg32]>; | Sched<[WriteFSReg32, ReadFSReg32, ReadFSReg32, ReadFSReg32]>; | ||||
| def FSRW : RVBTernaryR<0b10, 0b101, OPC_OP_32, "fsrw", | |||||
| "$rd, $rs1, $rs3, $rs2">, | |||||
| Sched<[WriteFSReg32, ReadFSReg32, ReadFSReg32, ReadFSReg32]>; | |||||
| def FSRIW : RVBTernaryImm5<0b10, 0b101, OPC_OP_IMM_32, | def FSRIW : RVBTernaryImm5<0b10, 0b101, OPC_OP_IMM_32, | ||||
| "fsriw", "$rd, $rs1, $rs3, $shamt">, | "fsriw", "$rd, $rs1, $rs3, $shamt">, | ||||
| Sched<[WriteFSRImm32, ReadFSRImm32, ReadFSRImm32]>; | Sched<[WriteFSRImm32, ReadFSRImm32, ReadFSRImm32]>; | ||||
| } // Predicates = [HasStdExtZbt, IsRV64] | } // Predicates = [HasStdExtZbt, IsRV64] | ||||
| let Predicates = [HasStdExtZbb] in { | let Predicates = [HasStdExtZbtOrZbpbo, IsRV64] in | ||||
| def FSRW : RVBTernaryR<0b10, 0b101, OPC_OP_32, "fsrw", | |||||
| "$rd, $rs1, $rs3, $rs2">, | |||||
| Sched<[WriteFSReg32, ReadFSReg32, ReadFSReg32, ReadFSReg32]>; | |||||
| let Predicates = [HasStdExtZbbOrZbpbo] in | |||||
Not Done ReplyInline ActionsCLZ only exist on RV32 for Zbpbo. Jim: CLZ only exist on RV32 for Zbpbo.
| |||||
| def CLZ : RVBUnary<0b0110000, 0b00000, 0b001, OPC_OP_IMM, "clz">, | def CLZ : RVBUnary<0b0110000, 0b00000, 0b001, OPC_OP_IMM, "clz">, | ||||
| Sched<[WriteCLZ, ReadCLZ]>; | Sched<[WriteCLZ, ReadCLZ]>; | ||||
| let Predicates = [HasStdExtZbb] in { | |||||
| def CTZ : RVBUnary<0b0110000, 0b00001, 0b001, OPC_OP_IMM, "ctz">, | def CTZ : RVBUnary<0b0110000, 0b00001, 0b001, OPC_OP_IMM, "ctz">, | ||||
| Sched<[WriteCTZ, ReadCTZ]>; | Sched<[WriteCTZ, ReadCTZ]>; | ||||
| def CPOP : RVBUnary<0b0110000, 0b00010, 0b001, OPC_OP_IMM, "cpop">, | def CPOP : RVBUnary<0b0110000, 0b00010, 0b001, OPC_OP_IMM, "cpop">, | ||||
| Sched<[WriteCPOP, ReadCPOP]>; | Sched<[WriteCPOP, ReadCPOP]>; | ||||
| } // Predicates = [HasStdExtZbb] | } // Predicates = [HasStdExtZbb] | ||||
| let Predicates = [HasStdExtZbb, IsRV64] in { | let Predicates = [HasStdExtZbb, IsRV64] in { | ||||
| def CLZW : RVBUnary<0b0110000, 0b00000, 0b001, OPC_OP_IMM_32, "clzw">, | def CLZW : RVBUnary<0b0110000, 0b00000, 0b001, OPC_OP_IMM_32, "clzw">, | ||||
| ▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines | |||||
| let Predicates = [HasStdExtZbcOrZbkc] in { | let Predicates = [HasStdExtZbcOrZbkc] in { | ||||
| def CLMUL : ALU_rr<0b0000101, 0b001, "clmul", /*Commutable*/1>, | def CLMUL : ALU_rr<0b0000101, 0b001, "clmul", /*Commutable*/1>, | ||||
| Sched<[WriteCLMUL, ReadCLMUL, ReadCLMUL]>; | Sched<[WriteCLMUL, ReadCLMUL, ReadCLMUL]>; | ||||
| def CLMULH : ALU_rr<0b0000101, 0b011, "clmulh", /*Commutable*/1>, | def CLMULH : ALU_rr<0b0000101, 0b011, "clmulh", /*Commutable*/1>, | ||||
| Sched<[WriteCLMUL, ReadCLMUL, ReadCLMUL]>; | Sched<[WriteCLMUL, ReadCLMUL, ReadCLMUL]>; | ||||
| } // Predicates = [HasStdExtZbcOrZbkc] | } // Predicates = [HasStdExtZbcOrZbkc] | ||||
| let Predicates = [HasStdExtZbb] in { | let Predicates = [HasStdExtZbbOrZbpbo] in { | ||||
| def MIN : ALU_rr<0b0000101, 0b100, "min", /*Commutable*/1>, | def MIN : ALU_rr<0b0000101, 0b100, "min", /*Commutable*/1>, | ||||
| Sched<[WriteIALU, ReadIALU, ReadIALU]>; | Sched<[WriteIALU, ReadIALU, ReadIALU]>; | ||||
| def MINU : ALU_rr<0b0000101, 0b101, "minu", /*Commutable*/1>, | |||||
| Sched<[WriteIALU, ReadIALU, ReadIALU]>; | |||||
| def MAX : ALU_rr<0b0000101, 0b110, "max", /*Commutable*/1>, | def MAX : ALU_rr<0b0000101, 0b110, "max", /*Commutable*/1>, | ||||
| Sched<[WriteIALU, ReadIALU, ReadIALU]>; | Sched<[WriteIALU, ReadIALU, ReadIALU]>; | ||||
| } // Predicates = [HasStdExtZbbOrZbpbo] | |||||
| let Predicates = [HasStdExtZbb] in { | |||||
| def MINU : ALU_rr<0b0000101, 0b101, "minu", /*Commutable*/1>, | |||||
| Sched<[WriteIALU, ReadIALU, ReadIALU]>; | |||||
| def MAXU : ALU_rr<0b0000101, 0b111, "maxu", /*Commutable*/1>, | def MAXU : ALU_rr<0b0000101, 0b111, "maxu", /*Commutable*/1>, | ||||
| Sched<[WriteIALU, ReadIALU, ReadIALU]>; | Sched<[WriteIALU, ReadIALU, ReadIALU]>; | ||||
| } // Predicates = [HasStdExtZbb] | } // Predicates = [HasStdExtZbb] | ||||
| let Predicates = [HasStdExtZbe] in { | let Predicates = [HasStdExtZbe] in { | ||||
| // NOTE: These mnemonics are from the 0.94 spec. There is a name conflict with | // NOTE: These mnemonics are from the 0.94 spec. There is a name conflict with | ||||
| // bext in the 0.93 spec. | // bext in the 0.93 spec. | ||||
| def BDECOMPRESS : ALU_rr<0b0100100, 0b110, "bdecompress">, | def BDECOMPRESS : ALU_rr<0b0100100, 0b110, "bdecompress">, | ||||
| Sched<[WriteDecompress, ReadDecompress, ReadDecompress]>; | Sched<[WriteDecompress, ReadDecompress, ReadDecompress]>; | ||||
| def BCOMPRESS : ALU_rr<0b0000100, 0b110, "bcompress">, | def BCOMPRESS : ALU_rr<0b0000100, 0b110, "bcompress">, | ||||
| Sched<[WriteCompress, ReadCompress, ReadCompress]>; | Sched<[WriteCompress, ReadCompress, ReadCompress]>; | ||||
| } // Predicates = [HasStdExtZbe] | } // Predicates = [HasStdExtZbe] | ||||
| let Predicates = [HasStdExtZbe, IsRV64] in { | let Predicates = [HasStdExtZbe, IsRV64] in { | ||||
| // NOTE: These mnemonics are from the 0.94 spec. There is a name conflict with | // NOTE: These mnemonics are from the 0.94 spec. There is a name conflict with | ||||
| // bextw in the 0.93 spec. | // bextw in the 0.93 spec. | ||||
| def BDECOMPRESSW : ALUW_rr<0b0100100, 0b110, "bdecompressw">, | def BDECOMPRESSW : ALUW_rr<0b0100100, 0b110, "bdecompressw">, | ||||
| Sched<[WriteDecompress32, ReadDecompress32, ReadDecompress32]>; | Sched<[WriteDecompress32, ReadDecompress32, ReadDecompress32]>; | ||||
| def BCOMPRESSW : ALUW_rr<0b0000100, 0b110, "bcompressw">, | def BCOMPRESSW : ALUW_rr<0b0000100, 0b110, "bcompressw">, | ||||
| Sched<[WriteCompress32, ReadCompress32, ReadCompress32]>; | Sched<[WriteCompress32, ReadCompress32, ReadCompress32]>; | ||||
| } // Predicates = [HasStdExtZbe, IsRV64] | } // Predicates = [HasStdExtZbe, IsRV64] | ||||
| let Predicates = [HasStdExtZbpOrZbkb] in { | let Predicates = [HasStdExtZbpOrZbkbOrZbpbo] in | ||||
| def PACK : ALU_rr<0b0000100, 0b100, "pack">, | def PACK : ALU_rr<0b0000100, 0b100, "pack">, | ||||
| Sched<[WritePACK, ReadPACK, ReadPACK]>; | Sched<[WritePACK, ReadPACK, ReadPACK]>; | ||||
| let Predicates = [HasStdExtZbpOrZbkb] in | |||||
| def PACKH : ALU_rr<0b0000100, 0b111, "packh">, | def PACKH : ALU_rr<0b0000100, 0b111, "packh">, | ||||
| Sched<[WritePACK, ReadPACK, ReadPACK]>; | Sched<[WritePACK, ReadPACK, ReadPACK]>; | ||||
| } // Predicates = [HasStdExtZbpOrZbkb] | |||||
| let Predicates = [HasStdExtZbpOrZbkb, IsRV64] in | let Predicates = [HasStdExtZbpOrZbkb, IsRV64] in | ||||
| def PACKW : ALUW_rr<0b0000100, 0b100, "packw">, | def PACKW : ALUW_rr<0b0000100, 0b100, "packw">, | ||||
| Sched<[WritePACK32, ReadPACK32, ReadPACK32]>; | Sched<[WritePACK32, ReadPACK32, ReadPACK32]>; | ||||
| let Predicates = [HasStdExtZbp] in | let Predicates = [HasStdExtZbpOrZbpbo] in | ||||
| def PACKU : ALU_rr<0b0100100, 0b100, "packu">, | def PACKU : ALU_rr<0b0100100, 0b100, "packu">, | ||||
| Sched<[WritePACKU, ReadPACKU, ReadPACKU]>; | Sched<[WritePACKU, ReadPACKU, ReadPACKU]>; | ||||
| let Predicates = [HasStdExtZbp, IsRV64] in | let Predicates = [HasStdExtZbp, IsRV64] in | ||||
| def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">, | def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">, | ||||
| Sched<[WritePACKU32, ReadPACKU32, ReadPACKU32]>; | Sched<[WritePACKU32, ReadPACKU32, ReadPACKU32]>; | ||||
| let Predicates = [HasStdExtZbm, IsRV64] in { | let Predicates = [HasStdExtZbm, IsRV64] in { | ||||
| ▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines | |||||
| } // Predicates = [HasStdExtZba, IsRV64] | } // Predicates = [HasStdExtZba, IsRV64] | ||||
| let Predicates = [HasStdExtZbp] in { | let Predicates = [HasStdExtZbp] in { | ||||
| def : InstAlias<"rev.p $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00001)>; | def : InstAlias<"rev.p $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00001)>; | ||||
| def : InstAlias<"rev2.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00010)>; | def : InstAlias<"rev2.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00010)>; | ||||
| def : InstAlias<"rev.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00011)>; | def : InstAlias<"rev.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00011)>; | ||||
| def : InstAlias<"rev4.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00100)>; | def : InstAlias<"rev4.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00100)>; | ||||
| def : InstAlias<"rev2.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00110)>; | def : InstAlias<"rev2.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00110)>; | ||||
| def : InstAlias<"rev8.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01000)>; | |||||
| def : InstAlias<"rev4.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01100)>; | def : InstAlias<"rev4.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01100)>; | ||||
| def : InstAlias<"rev2.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01110)>; | def : InstAlias<"rev2.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01110)>; | ||||
| def : InstAlias<"rev.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01111)>; | def : InstAlias<"rev.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01111)>; | ||||
| def : InstAlias<"rev.b $rd, $rs", (BREV8 GPR:$rd, GPR:$rs)>; | def : InstAlias<"rev.b $rd, $rs", (BREV8 GPR:$rd, GPR:$rs)>; | ||||
| def : InstAlias<"zip.n $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0001)>; | def : InstAlias<"zip.n $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0001)>; | ||||
| def : InstAlias<"unzip.n $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0001)>; | def : InstAlias<"unzip.n $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0001)>; | ||||
| def : InstAlias<"zip2.b $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0010)>; | def : InstAlias<"zip2.b $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0010)>; | ||||
| Show All 14 Lines | |||||
| def : InstAlias<"orc2.b $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00110)>; | def : InstAlias<"orc2.b $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00110)>; | ||||
| // orc.b is considered an instruction rather than an alias. | // orc.b is considered an instruction rather than an alias. | ||||
| def : InstAlias<"orc8.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01000)>; | def : InstAlias<"orc8.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01000)>; | ||||
| def : InstAlias<"orc4.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01100)>; | def : InstAlias<"orc4.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01100)>; | ||||
| def : InstAlias<"orc2.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01110)>; | def : InstAlias<"orc2.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01110)>; | ||||
| def : InstAlias<"orc.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01111)>; | def : InstAlias<"orc.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01111)>; | ||||
| } // Predicates = [HasStdExtZbp] | } // Predicates = [HasStdExtZbp] | ||||
| let Predicates = [HasStdExtZbpOrZbpbo] in | |||||
| def : InstAlias<"rev8.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01000)>; | |||||
| let Predicates = [HasStdExtZbp, IsRV32] in { | let Predicates = [HasStdExtZbp, IsRV32] in { | ||||
| def : InstAlias<"rev16 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b10000)>; | def : InstAlias<"rev16 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b10000)>; | ||||
| // rev8 is considered an instruction rather than an alias. | // rev8 is considered an instruction rather than an alias. | ||||
| def : InstAlias<"rev4 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11100)>; | def : InstAlias<"rev4 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11100)>; | ||||
| def : InstAlias<"rev2 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11110)>; | def : InstAlias<"rev2 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11110)>; | ||||
| def : InstAlias<"rev $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11111)>; | |||||
| def : InstAlias<"zip8 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1000)>; | def : InstAlias<"zip8 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1000)>; | ||||
| def : InstAlias<"unzip8 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1000)>; | def : InstAlias<"unzip8 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1000)>; | ||||
| def : InstAlias<"zip4 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1100)>; | def : InstAlias<"zip4 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1100)>; | ||||
| def : InstAlias<"unzip4 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1100)>; | def : InstAlias<"unzip4 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1100)>; | ||||
| def : InstAlias<"zip2 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1110)>; | def : InstAlias<"zip2 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1110)>; | ||||
| def : InstAlias<"unzip2 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1110)>; | def : InstAlias<"unzip2 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1110)>; | ||||
| // zip and unzip are considered instructions rather than an alias. | // zip and unzip are considered instructions rather than an alias. | ||||
| def : InstAlias<"orc16 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b10000)>; | def : InstAlias<"orc16 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b10000)>; | ||||
| def : InstAlias<"orc8 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11000)>; | def : InstAlias<"orc8 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11000)>; | ||||
| def : InstAlias<"orc4 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11100)>; | def : InstAlias<"orc4 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11100)>; | ||||
| def : InstAlias<"orc2 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11110)>; | def : InstAlias<"orc2 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11110)>; | ||||
| def : InstAlias<"orc $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11111)>; | def : InstAlias<"orc $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11111)>; | ||||
| } // Predicates = [HasStdExtZbp, IsRV32] | } // Predicates = [HasStdExtZbp, IsRV32] | ||||
| let Predicates = [HasStdExtZbpOrZbpbo, IsRV32] in | |||||
| def : InstAlias<"rev $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11111)>; | |||||
| let Predicates = [HasStdExtZbpOrZbpbo, IsRV64] in | |||||
| def : InstAlias<"rev $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111111)>; | |||||
| let Predicates = [HasStdExtZbp, IsRV64] in { | let Predicates = [HasStdExtZbp, IsRV64] in { | ||||
| def : InstAlias<"rev16.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b010000)>; | def : InstAlias<"rev16.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b010000)>; | ||||
| def : InstAlias<"rev8.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011000)>; | def : InstAlias<"rev8.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011000)>; | ||||
| def : InstAlias<"rev4.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011100)>; | def : InstAlias<"rev4.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011100)>; | ||||
| def : InstAlias<"rev2.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011110)>; | def : InstAlias<"rev2.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011110)>; | ||||
| def : InstAlias<"rev.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011111)>; | def : InstAlias<"rev.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011111)>; | ||||
| def : InstAlias<"rev32 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b100000)>; | def : InstAlias<"rev32 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b100000)>; | ||||
| def : InstAlias<"rev16 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b110000)>; | def : InstAlias<"rev16 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b110000)>; | ||||
| ▲ Show 20 Lines • Show All 171 Lines • ▼ Show 20 Lines | |||||
| } // Predicates = [HasStdExtZbpOrZbkb] | } // Predicates = [HasStdExtZbpOrZbkb] | ||||
| let Predicates = [HasStdExtZbpOrZbkb, IsRV32] in { | let Predicates = [HasStdExtZbpOrZbkb, IsRV32] in { | ||||
| // We treat zip and unzip as separate instructions, so match it directly. | // We treat zip and unzip as separate instructions, so match it directly. | ||||
| def : Pat<(i32 (riscv_shfl GPR:$rs1, 15)), (ZIP_RV32 GPR:$rs1)>; | def : Pat<(i32 (riscv_shfl GPR:$rs1, 15)), (ZIP_RV32 GPR:$rs1)>; | ||||
| def : Pat<(i32 (riscv_unshfl GPR:$rs1, 15)), (UNZIP_RV32 GPR:$rs1)>; | def : Pat<(i32 (riscv_unshfl GPR:$rs1, 15)), (UNZIP_RV32 GPR:$rs1)>; | ||||
| } // Predicates = [HasStdExtZbpOrZbkb, IsRV32] | } // Predicates = [HasStdExtZbpOrZbkb, IsRV32] | ||||
| let Predicates = [HasStdExtZbp] in { | let Predicates = [HasStdExtZbpOrZbpbo] in { | ||||
| def : PatGprGpr<riscv_grev, GREV>; | def : PatGprGpr<riscv_grev, GREV>; | ||||
| def : PatGprGpr<riscv_gorc, GORC>; | |||||
| def : PatGprImm<riscv_grev, GREVI, uimmlog2xlen>; | def : PatGprImm<riscv_grev, GREVI, uimmlog2xlen>; | ||||
| def : PatGprGpr<riscv_shfl, SHFL>; | |||||
| } // Predicates = [HasStdExtZbpOrZbpbo] | |||||
| let Predicates = [HasStdExtZbp] in { | |||||
| def : PatGprGpr<riscv_gorc, GORC>; | |||||
| def : PatGprImm<riscv_gorc, GORCI, uimmlog2xlen>; | def : PatGprImm<riscv_gorc, GORCI, uimmlog2xlen>; | ||||
| def : PatGprGpr<riscv_shfl, SHFL>; | |||||
| def : PatGprGpr<riscv_unshfl, UNSHFL>; | def : PatGprGpr<riscv_unshfl, UNSHFL>; | ||||
| def : PatGprImm<riscv_shfl, SHFLI, shfl_uimm>; | def : PatGprImm<riscv_shfl, SHFLI, shfl_uimm>; | ||||
| def : PatGprImm<riscv_unshfl, UNSHFLI, shfl_uimm>; | def : PatGprImm<riscv_unshfl, UNSHFLI, shfl_uimm>; | ||||
| def : PatGprGpr<int_riscv_xperm_n, XPERM4>; | def : PatGprGpr<int_riscv_xperm_n, XPERM4>; | ||||
| def : PatGprGpr<int_riscv_xperm_b, XPERM8>; | def : PatGprGpr<int_riscv_xperm_b, XPERM8>; | ||||
| def : PatGprGpr<int_riscv_xperm_h, XPERM_H>; | def : PatGprGpr<int_riscv_xperm_h, XPERM_H>; | ||||
| } // Predicates = [HasStdExtZbp] | } // Predicates = [HasStdExtZbp] | ||||
| Show All 24 Lines | |||||
| def : Pat<(i32 (riscv_grev GPR:$rs1, 24)), (REV8_RV32 GPR:$rs1)>; | def : Pat<(i32 (riscv_grev GPR:$rs1, 24)), (REV8_RV32 GPR:$rs1)>; | ||||
| } // Predicates = [HasStdExtZbp, IsRV32] | } // Predicates = [HasStdExtZbp, IsRV32] | ||||
| let Predicates = [HasStdExtZbp, IsRV64] in { | let Predicates = [HasStdExtZbp, IsRV64] in { | ||||
| // We treat rev8 as a separate instruction, so match it directly. | // We treat rev8 as a separate instruction, so match it directly. | ||||
| def : Pat<(i64 (riscv_grev GPR:$rs1, 56)), (REV8_RV64 GPR:$rs1)>; | def : Pat<(i64 (riscv_grev GPR:$rs1, 56)), (REV8_RV64 GPR:$rs1)>; | ||||
| } // Predicates = [HasStdExtZbp, IsRV64] | } // Predicates = [HasStdExtZbp, IsRV64] | ||||
| let Predicates = [HasStdExtZbt] in { | let Predicates = [HasStdExtZbtOrZbpbo] in { | ||||
| def : Pat<(or (and (not GPR:$rs2), GPR:$rs3), (and GPR:$rs2, GPR:$rs1)), | def : Pat<(or (and (not GPR:$rs2), GPR:$rs3), (and GPR:$rs2, GPR:$rs1)), | ||||
| (CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>; | (CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>; | ||||
| def : Pat<(xor (and (xor GPR:$rs1, GPR:$rs3), GPR:$rs2), GPR:$rs3), | def : Pat<(xor (and (xor GPR:$rs1, GPR:$rs3), GPR:$rs2), GPR:$rs3), | ||||
| (CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>; | (CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>; | ||||
| } // Predicates = [HasStdExtZbtOrZbpbo] | |||||
| let Predicates = [HasStdExtZbt] in { | |||||
| def : Pat<(select (XLenVT (setne GPR:$rs2, 0)), GPR:$rs1, GPR:$rs3), | def : Pat<(select (XLenVT (setne GPR:$rs2, 0)), GPR:$rs1, GPR:$rs3), | ||||
| (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>; | (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>; | ||||
| def : Pat<(select (XLenVT (seteq GPR:$rs2, 0)), GPR:$rs3, GPR:$rs1), | def : Pat<(select (XLenVT (seteq GPR:$rs2, 0)), GPR:$rs3, GPR:$rs1), | ||||
| (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>; | (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>; | ||||
| def : Pat<(select (XLenVT (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1, GPR:$rs3), | def : Pat<(select (XLenVT (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1, GPR:$rs3), | ||||
| (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>; | (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>; | ||||
| def : Pat<(select (XLenVT (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs3, GPR:$rs1), | def : Pat<(select (XLenVT (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs3, GPR:$rs1), | ||||
| (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>; | (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>; | ||||
| Show All 15 Lines | def : Pat<(select (XLenVT (setgt GPR:$x, simm12_minus1_nonzero:$imm)), GPR:$rs3, GPR:$rs1), | ||||
| (CMOV GPR:$rs1, (SLTI GPR:$x, (ImmPlus1 simm12_minus1_nonzero:$imm)), GPR:$rs3)>; | (CMOV GPR:$rs1, (SLTI GPR:$x, (ImmPlus1 simm12_minus1_nonzero:$imm)), GPR:$rs3)>; | ||||
| def : Pat<(select (XLenVT (setugt GPR:$x, simm12_minus1_nonzero:$imm)), GPR:$rs3, GPR:$rs1), | def : Pat<(select (XLenVT (setugt GPR:$x, simm12_minus1_nonzero:$imm)), GPR:$rs3, GPR:$rs1), | ||||
| (CMOV GPR:$rs1, (SLTIU GPR:$x, (ImmPlus1 simm12_minus1_nonzero:$imm)), GPR:$rs3)>; | (CMOV GPR:$rs1, (SLTIU GPR:$x, (ImmPlus1 simm12_minus1_nonzero:$imm)), GPR:$rs3)>; | ||||
| def : Pat<(select GPR:$rs2, GPR:$rs1, GPR:$rs3), | def : Pat<(select GPR:$rs2, GPR:$rs1, GPR:$rs3), | ||||
| (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>; | (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>; | ||||
| } // Predicates = [HasStdExtZbt] | } // Predicates = [HasStdExtZbt] | ||||
| let Predicates = [HasStdExtZbt] in { | let Predicates = [HasStdExtZbt] in | ||||
| def : Pat<(riscv_fsl GPR:$rs1, GPR:$rs3, GPR:$rs2), | def : Pat<(riscv_fsl GPR:$rs1, GPR:$rs3, GPR:$rs2), | ||||
| (FSL GPR:$rs1, GPR:$rs2, GPR:$rs3)>; | (FSL GPR:$rs1, GPR:$rs2, GPR:$rs3)>; | ||||
| let Predicates = [HasStdExtZbtOrZbpbo] in { | |||||
| def : Pat<(riscv_fsr GPR:$rs1, GPR:$rs3, GPR:$rs2), | def : Pat<(riscv_fsr GPR:$rs1, GPR:$rs3, GPR:$rs2), | ||||
| (FSR GPR:$rs1, GPR:$rs2, GPR:$rs3)>; | (FSR GPR:$rs1, GPR:$rs2, GPR:$rs3)>; | ||||
| def : Pat<(riscv_fsr GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt), | def : Pat<(riscv_fsr GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt), | ||||
| (FSRI GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt)>; | (FSRI GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt)>; | ||||
| // We can use FSRI for FSL by immediate if we subtract the immediate from | // We can use FSRI for FSL by immediate if we subtract the immediate from | ||||
| // XLen and swap the operands. | // XLen and swap the operands. | ||||
| def : Pat<(riscv_fsl GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt), | def : Pat<(riscv_fsl GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt), | ||||
| (FSRI GPR:$rs1, GPR:$rs3, (ImmSubFromXLen uimmlog2xlen:$shamt))>; | (FSRI GPR:$rs1, GPR:$rs3, (ImmSubFromXLen uimmlog2xlen:$shamt))>; | ||||
| } // Predicates = [HasStdExtZbt] | } // Predicates = [HasStdExtZbtOrZbpbo] | ||||
| let Predicates = [HasStdExtZbtOrZbpbo, IsRV64] in | |||||
| def : Pat<(riscv_fsrw GPR:$rs1, GPR:$rs3, GPR:$rs2), | |||||
| (FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>; | |||||
| let Predicates = [HasStdExtZbt, IsRV64] in { | let Predicates = [HasStdExtZbt, IsRV64] in { | ||||
| def : Pat<(riscv_fslw GPR:$rs1, GPR:$rs3, GPR:$rs2), | def : Pat<(riscv_fslw GPR:$rs1, GPR:$rs3, GPR:$rs2), | ||||
| (FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>; | (FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>; | ||||
| def : Pat<(riscv_fsrw GPR:$rs1, GPR:$rs3, GPR:$rs2), | |||||
| (FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>; | |||||
| def : Pat<(riscv_fsrw GPR:$rs1, GPR:$rs3, uimm5:$shamt), | def : Pat<(riscv_fsrw GPR:$rs1, GPR:$rs3, uimm5:$shamt), | ||||
| (FSRIW GPR:$rs1, GPR:$rs3, uimm5:$shamt)>; | (FSRIW GPR:$rs1, GPR:$rs3, uimm5:$shamt)>; | ||||
| // We can use FSRIW for FSLW by immediate if we subtract the immediate from | // We can use FSRIW for FSLW by immediate if we subtract the immediate from | ||||
| // 32 and swap the operands. | // 32 and swap the operands. | ||||
| def : Pat<(riscv_fslw GPR:$rs3, GPR:$rs1, uimm5:$shamt), | def : Pat<(riscv_fslw GPR:$rs3, GPR:$rs1, uimm5:$shamt), | ||||
| (FSRIW GPR:$rs1, GPR:$rs3, (ImmSubFrom32 uimm5:$shamt))>; | (FSRIW GPR:$rs1, GPR:$rs3, (ImmSubFrom32 uimm5:$shamt))>; | ||||
| } // Predicates = [HasStdExtZbt, IsRV64] | } // Predicates = [HasStdExtZbt, IsRV64] | ||||
| let Predicates = [HasStdExtZbb] in { | let Predicates = [HasStdExtZbbOrZbpbo] in | ||||
| def : PatGpr<ctlz, CLZ>; | def : PatGpr<ctlz, CLZ>; | ||||
| let Predicates = [HasStdExtZbb] in { | |||||
| def : PatGpr<cttz, CTZ>; | def : PatGpr<cttz, CTZ>; | ||||
| def : PatGpr<ctpop, CPOP>; | def : PatGpr<ctpop, CPOP>; | ||||
| } // Predicates = [HasStdExtZbb] | } // Predicates = [HasStdExtZbb] | ||||
| let Predicates = [HasStdExtZbb, IsRV64] in { | let Predicates = [HasStdExtZbb, IsRV64] in { | ||||
| def : PatGpr<riscv_clzw, CLZW>; | def : PatGpr<riscv_clzw, CLZW>; | ||||
| def : PatGpr<riscv_ctzw, CTZW>; | def : PatGpr<riscv_ctzw, CTZW>; | ||||
| def : Pat<(i64 (ctpop (i64 (zexti32 (i64 GPR:$rs1))))), (CPOPW GPR:$rs1)>; | def : Pat<(i64 (ctpop (i64 (zexti32 (i64 GPR:$rs1))))), (CPOPW GPR:$rs1)>; | ||||
| } // Predicates = [HasStdExtZbb, IsRV64] | } // Predicates = [HasStdExtZbb, IsRV64] | ||||
| let Predicates = [HasStdExtZbb] in { | let Predicates = [HasStdExtZbb] in { | ||||
| def : Pat<(sext_inreg GPR:$rs1, i8), (SEXT_B GPR:$rs1)>; | def : Pat<(sext_inreg GPR:$rs1, i8), (SEXT_B GPR:$rs1)>; | ||||
| def : Pat<(sext_inreg GPR:$rs1, i16), (SEXT_H GPR:$rs1)>; | def : Pat<(sext_inreg GPR:$rs1, i16), (SEXT_H GPR:$rs1)>; | ||||
| } // Predicates = [HasStdExtZbb] | } // Predicates = [HasStdExtZbb] | ||||
| let Predicates = [HasStdExtZbb] in { | let Predicates = [HasStdExtZbbOrZbpbo] in { | ||||
| def : PatGprGpr<smin, MIN>; | def : PatGprGpr<smin, MIN>; | ||||
| def : PatGprGpr<smax, MAX>; | def : PatGprGpr<smax, MAX>; | ||||
| } // Predicates = [HasStdExtZbbOrZbpbo] | |||||
| let Predicates = [HasStdExtZbb] in { | |||||
| def : PatGprGpr<umin, MINU>; | def : PatGprGpr<umin, MINU>; | ||||
| def : PatGprGpr<umax, MAXU>; | def : PatGprGpr<umax, MAXU>; | ||||
| } // Predicates = [HasStdExtZbb] | } // Predicates = [HasStdExtZbb] | ||||
| let Predicates = [HasStdExtZbbOrZbkb, IsRV32] in { | let Predicates = [HasStdExtZbbOrZbkb, IsRV32] in { | ||||
| def : Pat<(i32 (bswap GPR:$rs1)), (REV8_RV32 GPR:$rs1)>; | def : Pat<(i32 (bswap GPR:$rs1)), (REV8_RV32 GPR:$rs1)>; | ||||
| } // Predicates = [HasStdExtZbbOrZbkb, IsRV32] | } // Predicates = [HasStdExtZbbOrZbkb, IsRV32] | ||||
| let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in { | let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in { | ||||
| def : Pat<(i64 (bswap GPR:$rs1)), (REV8_RV64 GPR:$rs1)>; | def : Pat<(i64 (bswap GPR:$rs1)), (REV8_RV64 GPR:$rs1)>; | ||||
| } // Predicates = [HasStdExtZbbOrZbkb, IsRV64] | } // Predicates = [HasStdExtZbbOrZbkb, IsRV64] | ||||
| let Predicates = [HasStdExtZbpOrZbkb] in { | let Predicates = [HasStdExtZbpOrZbkb] in { | ||||
| def : Pat<(or (and (shl GPR:$rs2, (XLenVT 8)), 0xFFFF), | def : Pat<(or (and (shl GPR:$rs2, (XLenVT 8)), 0xFFFF), | ||||
| (and GPR:$rs1, 0x00FF)), | (and GPR:$rs1, 0x00FF)), | ||||
| (PACKH GPR:$rs1, GPR:$rs2)>; | (PACKH GPR:$rs1, GPR:$rs2)>; | ||||
| def : Pat<(or (shl (and GPR:$rs2, 0x00FF), (XLenVT 8)), | def : Pat<(or (shl (and GPR:$rs2, 0x00FF), (XLenVT 8)), | ||||
| (and GPR:$rs1, 0x00FF)), | (and GPR:$rs1, 0x00FF)), | ||||
| (PACKH GPR:$rs1, GPR:$rs2)>; | (PACKH GPR:$rs1, GPR:$rs2)>; | ||||
| } // Predicates = [HasStdExtZbpOrZbkb] | } // Predicates = [HasStdExtZbpOrZbkb] | ||||
| let Predicates = [HasStdExtZbpOrZbkb, IsRV32] in | let Predicates = [HasStdExtZbpOrZbkbOrZbpbo, IsRV32] in | ||||
| def : Pat<(i32 (or (and GPR:$rs1, 0x0000FFFF), (shl GPR:$rs2, (i32 16)))), | def : Pat<(i32 (or (and GPR:$rs1, 0x0000FFFF), (shl GPR:$rs2, (i32 16)))), | ||||
| (PACK GPR:$rs1, GPR:$rs2)>; | (PACK GPR:$rs1, GPR:$rs2)>; | ||||
| let Predicates = [HasStdExtZbpOrZbkb, IsRV64] in { | let Predicates = [HasStdExtZbpOrZbkbOrZbpbo, IsRV64] in | ||||
| def : Pat<(i64 (or (and GPR:$rs1, 0x00000000FFFFFFFF), (shl GPR:$rs2, (i64 32)))), | def : Pat<(i64 (or (and GPR:$rs1, 0x00000000FFFFFFFF), (shl GPR:$rs2, (i64 32)))), | ||||
| (PACK GPR:$rs1, GPR:$rs2)>; | (PACK GPR:$rs1, GPR:$rs2)>; | ||||
| let Predicates = [HasStdExtZbpOrZbkb, IsRV64] in { | |||||
| def : Pat<(i64 (sext_inreg (or (shl GPR:$rs2, (i64 16)), | def : Pat<(i64 (sext_inreg (or (shl GPR:$rs2, (i64 16)), | ||||
| (and GPR:$rs1, 0x000000000000FFFF)), | (and GPR:$rs1, 0x000000000000FFFF)), | ||||
| i32)), | i32)), | ||||
| (PACKW GPR:$rs1, GPR:$rs2)>; | (PACKW GPR:$rs1, GPR:$rs2)>; | ||||
| def : Pat<(i64 (or (sext_inreg (shl GPR:$rs2, (i64 16)), i32), | def : Pat<(i64 (or (sext_inreg (shl GPR:$rs2, (i64 16)), i32), | ||||
| (and GPR:$rs1, 0x000000000000FFFF))), | (and GPR:$rs1, 0x000000000000FFFF))), | ||||
| (PACKW GPR:$rs1, GPR:$rs2)>; | (PACKW GPR:$rs1, GPR:$rs2)>; | ||||
| } // Predicates = [HasStdExtZbpOrZbkb, IsRV64] | } // Predicates = [HasStdExtZbpOrZbkb, IsRV64] | ||||
| let Predicates = [HasStdExtZbp, IsRV32] in | let Predicates = [HasStdExtZbpOrZbpbo, IsRV32] in | ||||
| def : Pat<(i32 (or (and GPR:$rs2, 0xFFFF0000), (srl GPR:$rs1, (i32 16)))), | def : Pat<(i32 (or (and GPR:$rs2, 0xFFFF0000), (srl GPR:$rs1, (i32 16)))), | ||||
| (PACKU GPR:$rs1, GPR:$rs2)>; | (PACKU GPR:$rs1, GPR:$rs2)>; | ||||
| let Predicates = [HasStdExtZbp, IsRV64] in { | let Predicates = [HasStdExtZbpOrZbpbo, IsRV64] in | ||||
| def : Pat<(i64 (or (and GPR:$rs2, 0xFFFFFFFF00000000), (srl GPR:$rs1, (i64 32)))), | def : Pat<(i64 (or (and GPR:$rs2, 0xFFFFFFFF00000000), (srl GPR:$rs1, (i64 32)))), | ||||
| (PACKU GPR:$rs1, GPR:$rs2)>; | (PACKU GPR:$rs1, GPR:$rs2)>; | ||||
| let Predicates = [HasStdExtZbp, IsRV64] in | |||||
| def : Pat<(i64 (or (and (assertsexti32 GPR:$rs2), 0xFFFFFFFFFFFF0000), | def : Pat<(i64 (or (and (assertsexti32 GPR:$rs2), 0xFFFFFFFFFFFF0000), | ||||
| (srl (and GPR:$rs1, 0xFFFFFFFF), (i64 16)))), | (srl (and GPR:$rs1, 0xFFFFFFFF), (i64 16)))), | ||||
| (PACKUW GPR:$rs1, GPR:$rs2)>; | (PACKUW GPR:$rs1, GPR:$rs2)>; | ||||
| } // Predicates = [HasStdExtZbp, IsRV64] | |||||
| let Predicates = [HasStdExtZbbOrZbp, IsRV32] in | let Predicates = [HasStdExtZbbOrZbp, IsRV32] in | ||||
| def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (ZEXT_H_RV32 GPR:$rs)>; | def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (ZEXT_H_RV32 GPR:$rs)>; | ||||
| let Predicates = [HasStdExtZbbOrZbp, IsRV64] in | let Predicates = [HasStdExtZbbOrZbp, IsRV64] in | ||||
| def : Pat<(i64 (and GPR:$rs, 0xFFFF)), (ZEXT_H_RV64 GPR:$rs)>; | def : Pat<(i64 (and GPR:$rs, 0xFFFF)), (ZEXT_H_RV64 GPR:$rs)>; | ||||
| let Predicates = [HasStdExtZba] in { | let Predicates = [HasStdExtZba] in { | ||||
| def : Pat<(add (shl GPR:$rs1, (XLenVT 1)), non_imm12:$rs2), | def : Pat<(add (shl GPR:$rs1, (XLenVT 1)), non_imm12:$rs2), | ||||
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FSR and FSRI only exist on RV32 for Zbpbo.