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mlir/test/Conversion/MemRefToSPIRV/alloc.mlir
| Show All 35 Lines | func.func @alloc_dealloc_workgroup_mem(%arg0 : index, %arg1 : index) { | ||||
| memref.store %1, %0[%arg0, %arg1] : memref<4x5xi16, 3> | memref.store %1, %0[%arg0, %arg1] : memref<4x5xi16, 3> | ||||
| memref.dealloc %0 : memref<4x5xi16, 3> | memref.dealloc %0 : memref<4x5xi16, 3> | ||||
| return | return | ||||
| } | } | ||||
| } | } | ||||
| // CHECK: spv.GlobalVariable @__workgroup_mem__{{[0-9]+}} | // CHECK: spv.GlobalVariable @__workgroup_mem__{{[0-9]+}} | ||||
| // CHECK-SAME: !spv.ptr<!spv.struct<(!spv.array<20 x i32>)>, Workgroup> | // CHECK-SAME: !spv.ptr<!spv.struct<(!spv.array<20 x i32>)>, Workgroup> | ||||
| // CHECK_LABEL: spv.func @alloc_dealloc_workgroup_mem | // CHECK: func @alloc_dealloc_workgroup_mem | ||||
| // CHECK: %[[VAR:.+]] = spv.mlir.addressof @__workgroup_mem__0 | // CHECK: %[[VAR:.+]] = spv.mlir.addressof @__workgroup_mem__0 | ||||
| // CHECK: %[[LOC:.+]] = spv.SDiv | // CHECK: %[[LOC:.+]] = spv.SDiv | ||||
| // CHECK: %[[PTR:.+]] = spv.AccessChain %[[VAR]][%{{.+}}, %[[LOC]]] | // CHECK: %[[PTR:.+]] = spv.AccessChain %[[VAR]][%{{.+}}, %[[LOC]]] | ||||
| // CHECK: %{{.+}} = spv.Load "Workgroup" %[[PTR]] : i32 | // CHECK: %{{.+}} = spv.Load "Workgroup" %[[PTR]] : i32 | ||||
| // CHECK: %[[LOC:.+]] = spv.SDiv | // CHECK: %[[LOC:.+]] = spv.SDiv | ||||
| // CHECK: %[[PTR:.+]] = spv.AccessChain %[[VAR]][%{{.+}}, %[[LOC]]] | // CHECK: %[[PTR:.+]] = spv.AccessChain %[[VAR]][%{{.+}}, %[[LOC]]] | ||||
| // CHECK: %{{.+}} = spv.AtomicAnd "Workgroup" "AcquireRelease" %[[PTR]], %{{.+}} : !spv.ptr<i32, Workgroup> | // CHECK: %{{.+}} = spv.AtomicAnd "Workgroup" "AcquireRelease" %[[PTR]], %{{.+}} : !spv.ptr<i32, Workgroup> | ||||
| // CHECK: %{{.+}} = spv.AtomicOr "Workgroup" "AcquireRelease" %[[PTR]], %{{.+}} : !spv.ptr<i32, Workgroup> | // CHECK: %{{.+}} = spv.AtomicOr "Workgroup" "AcquireRelease" %[[PTR]], %{{.+}} : !spv.ptr<i32, Workgroup> | ||||
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