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llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
Show First 20 Lines • Show All 695 Lines • ▼ Show 20 Lines | BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const { | ||||
} | } | ||||
// On GFX908, in order to guarantee copying between AGPRs, we need a scratch | // On GFX908, in order to guarantee copying between AGPRs, we need a scratch | ||||
// VGPR available at all times. | // VGPR available at all times. | ||||
if (ST.hasMAIInsts() && !ST.hasGFX90AInsts()) { | if (ST.hasMAIInsts() && !ST.hasGFX90AInsts()) { | ||||
reserveRegisterTuples(Reserved, MFI->getVGPRForAGPRCopy()); | reserveRegisterTuples(Reserved, MFI->getVGPRForAGPRCopy()); | ||||
} | } | ||||
for (Register Reg : MFI->WWMReservedRegs) | for (Register Reg : MFI->getWWMReservedRegs()) | ||||
reserveRegisterTuples(Reserved, Reg); | reserveRegisterTuples(Reserved, Reg); | ||||
// FIXME: Stop using reserved registers for this. | // FIXME: Stop using reserved registers for this. | ||||
for (MCPhysReg Reg : MFI->getAGPRSpillVGPRs()) | for (MCPhysReg Reg : MFI->getAGPRSpillVGPRs()) | ||||
reserveRegisterTuples(Reserved, Reg); | reserveRegisterTuples(Reserved, Reg); | ||||
for (MCPhysReg Reg : MFI->getVGPRSpillAGPRs()) | for (MCPhysReg Reg : MFI->getVGPRSpillAGPRs()) | ||||
reserveRegisterTuples(Reserved, Reg); | reserveRegisterTuples(Reserved, Reg); | ||||
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