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llvm/lib/Target/AArch64/AArch64.td
| Show First 20 Lines • Show All 707 Lines • ▼ Show 20 Lines | |||||
| def TuneX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1", | def TuneX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1", | ||||
| "Cortex-X1 ARM processors", [ | "Cortex-X1 ARM processors", [ | ||||
| FeatureCmpBccFusion, | FeatureCmpBccFusion, | ||||
| FeatureFuseAES, | FeatureFuseAES, | ||||
| FeaturePostRAScheduler]>; | FeaturePostRAScheduler]>; | ||||
| def TuneX2 : SubtargetFeature<"cortex-x2", "ARMProcFamily", "CortexX2", | def TuneX2 : SubtargetFeature<"cortex-x2", "ARMProcFamily", "CortexX2", | ||||
| "Cortex-X2 ARM processors", [ | "Cortex-X2 ARM processors", [ | ||||
| FeatureFuseAES, | FeatureFuseAES, | ||||
dmgreen: This can be the same as TuneX1. It might be worth using the same TuneX1 in both the cortex-x1… | |||||
| FeaturePostRAScheduler, | FeaturePostRAScheduler, | ||||
| FeatureCmpBccFusion]>; | FeatureCmpBccFusion]>; | ||||
| def TuneA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX", | def TuneA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX", | ||||
| "Fujitsu A64FX processors", [ | "Fujitsu A64FX processors", [ | ||||
| FeaturePostRAScheduler, | FeaturePostRAScheduler, | ||||
| FeatureAggressiveFMA, | FeatureAggressiveFMA, | ||||
| FeatureArithmeticBccFusion, | FeatureArithmeticBccFusion, | ||||
| ▲ Show 20 Lines • Show All 242 Lines • ▼ Show 20 Lines | list<SubtargetFeature> A710 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, | ||||
| FeatureETE, FeatureMTE, FeatureFP16FML, | FeatureETE, FeatureMTE, FeatureFP16FML, | ||||
| FeatureSVE2BitPerm, FeatureBF16, FeatureMatMulInt8]; | FeatureSVE2BitPerm, FeatureBF16, FeatureMatMulInt8]; | ||||
| list<SubtargetFeature> R82 = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16, | list<SubtargetFeature> R82 = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16, | ||||
| FeatureFP16FML, FeatureSSBS, FeaturePredRes, | FeatureFP16FML, FeatureSSBS, FeaturePredRes, | ||||
| FeatureSB, FeatureSpecRestrict]; | FeatureSB, FeatureSpecRestrict]; | ||||
| list<SubtargetFeature> X1 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, | list<SubtargetFeature> X1 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, | ||||
| FeatureNEON, FeatureRCPC, FeaturePerfMon, | FeatureNEON, FeatureRCPC, FeaturePerfMon, | ||||
| FeatureSPE, FeatureFullFP16, FeatureDotProd]; | FeatureSPE, FeatureFullFP16, FeatureDotProd]; | ||||
| list<SubtargetFeature> X1C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, | |||||
| FeatureNEON, FeatureRCPC, FeaturePerfMon, | |||||
| FeatureSPE, FeatureFullFP16, FeatureDotProd, | |||||
Should this have dotprod and RCPC? The TRM isn't super clear on what features are present. Is FP16FML present? dmgreen: Should this have dotprod and RCPC?
The TRM isn't super clear on what features are present. Is… | |||||
Right, the addition of FP16FML must have been copied from the X1, which was later removed when upstreaming. I removed it here, and I added dotard and RCPC. The only relevant change from X1 to X1C is the addition of PAUTH, as per the TRM. stuij: Right, the addition of FP16FML must have been copied from the X1, which was later removed when… | |||||
| FeaturePAuth]; | |||||
| list<SubtargetFeature> X2 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, | list<SubtargetFeature> X2 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, | ||||
| FeatureMatMulInt8, FeatureBF16, FeatureAM, | FeatureMatMulInt8, FeatureBF16, FeatureAM, | ||||
| FeatureMTE, FeatureETE, FeatureSVE2BitPerm, | FeatureMTE, FeatureETE, FeatureSVE2BitPerm, | ||||
| FeatureFP16FML]; | FeatureFP16FML]; | ||||
| list<SubtargetFeature> A64FX = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON, | list<SubtargetFeature> A64FX = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON, | ||||
| FeatureSHA2, FeaturePerfMon, FeatureFullFP16, | FeatureSHA2, FeaturePerfMon, FeatureFullFP16, | ||||
| FeatureSVE, FeatureComplxNum]; | FeatureSVE, FeatureComplxNum]; | ||||
| list<SubtargetFeature> Carmel = [HasV8_2aOps, FeatureNEON, FeatureCrypto, | list<SubtargetFeature> Carmel = [HasV8_2aOps, FeatureNEON, FeatureCrypto, | ||||
| ▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines | |||||
| def : ProcessorModel<"cortex-a78c", CortexA57Model, ProcessorFeatures.A78C, | def : ProcessorModel<"cortex-a78c", CortexA57Model, ProcessorFeatures.A78C, | ||||
| [TuneA78C]>; | [TuneA78C]>; | ||||
| def : ProcessorModel<"cortex-a710", CortexA57Model, ProcessorFeatures.A710, | def : ProcessorModel<"cortex-a710", CortexA57Model, ProcessorFeatures.A710, | ||||
| [TuneA710]>; | [TuneA710]>; | ||||
| def : ProcessorModel<"cortex-r82", CortexA55Model, ProcessorFeatures.R82, | def : ProcessorModel<"cortex-r82", CortexA55Model, ProcessorFeatures.R82, | ||||
| [TuneR82]>; | [TuneR82]>; | ||||
| def : ProcessorModel<"cortex-x1", CortexA57Model, ProcessorFeatures.X1, | def : ProcessorModel<"cortex-x1", CortexA57Model, ProcessorFeatures.X1, | ||||
| [TuneX1]>; | [TuneX1]>; | ||||
| def : ProcessorModel<"cortex-x1c", CortexA57Model, ProcessorFeatures.X1C, | |||||
| [TuneX1]>; | |||||
| def : ProcessorModel<"cortex-x2", CortexA57Model, ProcessorFeatures.X2, | def : ProcessorModel<"cortex-x2", CortexA57Model, ProcessorFeatures.X2, | ||||
| [TuneX2]>; | [TuneX2]>; | ||||
| def : ProcessorModel<"neoverse-e1", CortexA53Model, | def : ProcessorModel<"neoverse-e1", CortexA53Model, | ||||
| ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>; | ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>; | ||||
| def : ProcessorModel<"neoverse-n1", CortexA57Model, | def : ProcessorModel<"neoverse-n1", CortexA57Model, | ||||
| ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>; | ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>; | ||||
| def : ProcessorModel<"neoverse-n2", CortexA57Model, | def : ProcessorModel<"neoverse-n2", CortexA57Model, | ||||
| ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>; | ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>; | ||||
| ▲ Show 20 Lines • Show All 131 Lines • Show Last 20 Lines | |||||
This can be the same as TuneX1. It might be worth using the same TuneX1 in both the cortex-x1 and cortex-x1c.