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Differential D117318 Diff 403203 llvm/lib/Target/RISCV/RISCVCallLowering.cpp

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llvm/lib/Target/RISCV/RISCVCallLowering.cpp

//===-- RISCVCallLowering.cpp - Call lowering -------------------*- C++ -*-===// //===-- RISCVCallLowering.cpp - Call lowering -------------------*- C++ -*-===//
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
/// \file /// \file
/// This file implements the lowering of LLVM calls to machine code calls for /// This file implements the lowering of LLVM calls to machine code calls for
/// GlobalISel. /// GlobalISel.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "RISCVCallLowering.h" #include "RISCVCallLowering.h"
#include "RISCVISelLowering.h" #include "RISCVISelLowering.h"
#include "RISCVSubtarget.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
using namespace llvm; using namespace llvm;
namespace {
struct RISCVOutgoingValueAssigner : public CallLowering::OutgoingValueAssigner {
private:
// The function used internally to assign args - we ignore the AssignFn stored
// by OutgoingValueAssigner since RISC-V implements its CC using a custom
// function with a different signature.
RISCVTargetLowering::RISCVCCAssignFn *RISCVAssignFn;
// Whether this is assigning args for a return.
bool IsRet;
public:
RISCVOutgoingValueAssigner(
RISCVTargetLowering::RISCVCCAssignFn *RISCVAssignFn_, bool IsRet)
: CallLowering::OutgoingValueAssigner(nullptr),
RISCVAssignFn(RISCVAssignFn_), IsRet(IsRet) {}
bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo,
const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
CCState &State) override {
MachineFunction &MF = State.getMachineFunction();
const DataLayout &DL = MF.getDataLayout();
const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
return RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT,
LocInfo, Flags, State, /*IsFixed=*/true, IsRet,
Info.Ty, *Subtarget.getTargetLowering(),
/*FirstMaskArgument=*/None);
}
};
struct RISCVOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
RISCVOutgoingValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
MachineInstrBuilder MIB)
: OutgoingValueHandler(B, MRI), MIB(MIB) {}
MachineInstrBuilder MIB;
Register getStackAddress(uint64_t MemSize, int64_t Offset,
MachinePointerInfo &MPO,
ISD::ArgFlagsTy Flags) override {
llvm_unreachable("not implemented");
}
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
MachinePointerInfo &MPO, CCValAssign &VA) override {
llvm_unreachable("not implemented");
}
void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override {
Register ExtReg = extendRegister(ValVReg, VA);
MIRBuilder.buildCopy(PhysReg, ExtReg);
MIB.addUse(PhysReg, RegState::Implicit);
}
};
} // namespace
RISCVCallLowering::RISCVCallLowering(const RISCVTargetLowering &TLI) RISCVCallLowering::RISCVCallLowering(const RISCVTargetLowering &TLI)
: CallLowering(&TLI) {} : CallLowering(&TLI) {}
bool RISCVCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
const Value *Val,
ArrayRef<Register> VRegs,
MachineInstrBuilder &Ret) const {
if (!Val)
return true;
// TODO: Only integer, pointer and aggregate types are supported now.
if (!Val->getType()->isIntOrPtrTy() && !Val->getType()->isAggregateType())
return false;
MachineFunction &MF = MIRBuilder.getMF();
const DataLayout &DL = MF.getDataLayout();
const Function &F = MF.getFunction();
CallingConv::ID CC = F.getCallingConv();
ArgInfo OrigRetInfo(VRegs, Val->getType(), 0);
setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);
SmallVector<ArgInfo, 4> SplitRetInfos;
splitToValueTypes(OrigRetInfo, SplitRetInfos, DL, CC);
RISCVOutgoingValueAssigner Assigner(
CC == CallingConv::Fast ? RISCV::CC_RISCV_FastCC : RISCV::CC_RISCV,
/*IsRet=*/true);
RISCVOutgoingValueHandler Handler(MIRBuilder, MF.getRegInfo(), Ret);
return determineAndHandleAssignments(Handler, Assigner, SplitRetInfos,
MIRBuilder, CC, F.isVarArg());
}
arsenmUnsubmitted
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This looks like you're copying the broken form of splitToValueTypes from x86. I think trying to handle all of the argument marshalling in simple looking callbacks like this is unworkable. If you call the generic splitToValueTypes in CallLowering, it should try to handle everything for you

arsenm: This looks like you're copying the broken form of splitToValueTypes from x86. I think trying to…
bool RISCVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, bool RISCVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
const Value *Val, ArrayRef<Register> VRegs, const Value *Val, ArrayRef<Register> VRegs,
FunctionLoweringInfo &FLI) const { FunctionLoweringInfo &FLI) const {
assert(!Val == VRegs.empty() && "Return value without a vreg");
MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(RISCV::PseudoRET); MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(RISCV::PseudoRET);
if (Val != nullptr) { if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))
return false; return false;
}
MIRBuilder.insertInstr(Ret); MIRBuilder.insertInstr(Ret);
return true; return true;
} }
bool RISCVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, bool RISCVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
const Function &F, const Function &F,
ArrayRef<ArrayRef<Register>> VRegs, ArrayRef<ArrayRef<Register>> VRegs,
FunctionLoweringInfo &FLI) const { FunctionLoweringInfo &FLI) const {
if (F.arg_empty()) if (F.arg_empty())
return true; return true;
return false; return false;
} }
bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
CallLoweringInfo &Info) const { CallLoweringInfo &Info) const {
return false; return false;
} }
arsenmUnsubmitted
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This is reinventing generic infrastructure

arsenm: This is reinventing generic infrastructure
arsenmUnsubmitted
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Ditto, this is a less complete copy of the generic infrastructure

arsenm: Ditto, this is a less complete copy of the generic infrastructure
arsenmUnsubmitted
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Ditto

arsenm: Ditto