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Differential D117947 Diff 402952 llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll

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llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-V
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: llc -mtriple=riscv32 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,ZVE64X
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-V
; RUN: llc -mtriple=riscv64 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,ZVE64X
define <vscale x 1 x i8> @vremu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) { define <vscale x 1 x i8> @vremu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
; CHECK-LABEL: vremu_vv_nxv1i8: ; CHECK-LABEL: vremu_vv_nxv1i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: vremu.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = urem <vscale x 1 x i8> %va, %vb %vc = urem <vscale x 1 x i8> %va, %vb
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; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0 %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%vc = urem <vscale x 1 x i64> %va, %splat %vc = urem <vscale x 1 x i64> %va, %splat
ret <vscale x 1 x i64> %vc ret <vscale x 1 x i64> %vc
} }
define <vscale x 1 x i64> @vremu_vi_nxv1i64_0(<vscale x 1 x i64> %va) { define <vscale x 1 x i64> @vremu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
; RV32-LABEL: vremu_vi_nxv1i64_0: ; RV32-V-LABEL: vremu_vi_nxv1i64_0:
; RV32: # %bb.0: ; RV32-V: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: lui a0, 131072 ; RV32-V-NEXT: lui a0, 131072
; RV32-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: sw a0, 12(sp)
; RV32-NEXT: li a0, 1 ; RV32-V-NEXT: li a0, 1
; RV32-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-V-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-V-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vmulhu.vv v9, v8, v9 ; RV32-V-NEXT: vmulhu.vv v9, v8, v9
; RV32-NEXT: li a0, 61 ; RV32-V-NEXT: li a0, 61
; RV32-NEXT: vsrl.vx v9, v9, a0 ; RV32-V-NEXT: vsrl.vx v9, v9, a0
; RV32-NEXT: li a0, -7 ; RV32-V-NEXT: li a0, -7
; RV32-NEXT: vnmsac.vx v8, a0, v9 ; RV32-V-NEXT: vnmsac.vx v8, a0, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-V-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-V-NEXT: ret
; ;
; RV64-LABEL: vremu_vi_nxv1i64_0: ; ZVE64X-LABEL: vremu_vi_nxv1i64_0:
; RV64: # %bb.0: ; ZVE64X: # %bb.0:
; RV64-NEXT: li a0, 1 ; ZVE64X-NEXT: li a0, -7
; RV64-NEXT: slli a0, a0, 61 ; ZVE64X-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV64-NEXT: addi a0, a0, 1 ; ZVE64X-NEXT: vremu.vx v8, v8, a0
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; ZVE64X-NEXT: ret
; RV64-NEXT: vmulhu.vx v9, v8, a0 ;
; RV64-NEXT: li a0, 61 ; RV64-V-LABEL: vremu_vi_nxv1i64_0:
; RV64-NEXT: vsrl.vx v9, v9, a0 ; RV64-V: # %bb.0:
; RV64-NEXT: li a0, -7 ; RV64-V-NEXT: li a0, 1
; RV64-NEXT: vnmsac.vx v8, a0, v9 ; RV64-V-NEXT: slli a0, a0, 61
; RV64-NEXT: ret ; RV64-V-NEXT: addi a0, a0, 1
; RV64-V-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV64-V-NEXT: vmulhu.vx v9, v8, a0
; RV64-V-NEXT: li a0, 61
; RV64-V-NEXT: vsrl.vx v9, v9, a0
; RV64-V-NEXT: li a0, -7
; RV64-V-NEXT: vnmsac.vx v8, a0, v9
; RV64-V-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0 %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%vc = urem <vscale x 1 x i64> %va, %splat %vc = urem <vscale x 1 x i64> %va, %splat
ret <vscale x 1 x i64> %vc ret <vscale x 1 x i64> %vc
} }
; fold (urem x, pow2) -> (and x, pow2-1) ; fold (urem x, pow2) -> (and x, pow2-1)
define <vscale x 1 x i64> @vremu_vi_nxv1i64_1(<vscale x 1 x i64> %va) { define <vscale x 1 x i64> @vremu_vi_nxv1i64_1(<vscale x 1 x i64> %va) {
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; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0 %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%vc = urem <vscale x 2 x i64> %va, %splat %vc = urem <vscale x 2 x i64> %va, %splat
ret <vscale x 2 x i64> %vc ret <vscale x 2 x i64> %vc
} }
define <vscale x 2 x i64> @vremu_vi_nxv2i64_0(<vscale x 2 x i64> %va) { define <vscale x 2 x i64> @vremu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
; RV32-LABEL: vremu_vi_nxv2i64_0: ; RV32-V-LABEL: vremu_vi_nxv2i64_0:
; RV32: # %bb.0: ; RV32-V: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: lui a0, 131072 ; RV32-V-NEXT: lui a0, 131072
; RV32-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: sw a0, 12(sp)
; RV32-NEXT: li a0, 1 ; RV32-V-NEXT: li a0, 1
; RV32-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; RV32-V-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-V-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmulhu.vv v10, v8, v10 ; RV32-V-NEXT: vmulhu.vv v10, v8, v10
; RV32-NEXT: li a0, 61 ; RV32-V-NEXT: li a0, 61
; RV32-NEXT: vsrl.vx v10, v10, a0 ; RV32-V-NEXT: vsrl.vx v10, v10, a0
; RV32-NEXT: li a0, -7 ; RV32-V-NEXT: li a0, -7
; RV32-NEXT: vnmsac.vx v8, a0, v10 ; RV32-V-NEXT: vnmsac.vx v8, a0, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-V-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-V-NEXT: ret
; ;
; RV64-LABEL: vremu_vi_nxv2i64_0: ; ZVE64X-LABEL: vremu_vi_nxv2i64_0:
; RV64: # %bb.0: ; ZVE64X: # %bb.0:
; RV64-NEXT: li a0, 1 ; ZVE64X-NEXT: li a0, -7
; RV64-NEXT: slli a0, a0, 61 ; ZVE64X-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV64-NEXT: addi a0, a0, 1 ; ZVE64X-NEXT: vremu.vx v8, v8, a0
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; ZVE64X-NEXT: ret
; RV64-NEXT: vmulhu.vx v10, v8, a0 ;
; RV64-NEXT: li a0, 61 ; RV64-V-LABEL: vremu_vi_nxv2i64_0:
; RV64-NEXT: vsrl.vx v10, v10, a0 ; RV64-V: # %bb.0:
; RV64-NEXT: li a0, -7 ; RV64-V-NEXT: li a0, 1
; RV64-NEXT: vnmsac.vx v8, a0, v10 ; RV64-V-NEXT: slli a0, a0, 61
; RV64-NEXT: ret ; RV64-V-NEXT: addi a0, a0, 1
; RV64-V-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV64-V-NEXT: vmulhu.vx v10, v8, a0
; RV64-V-NEXT: li a0, 61
; RV64-V-NEXT: vsrl.vx v10, v10, a0
; RV64-V-NEXT: li a0, -7
; RV64-V-NEXT: vnmsac.vx v8, a0, v10
; RV64-V-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0 %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%vc = urem <vscale x 2 x i64> %va, %splat %vc = urem <vscale x 2 x i64> %va, %splat
ret <vscale x 2 x i64> %vc ret <vscale x 2 x i64> %vc
} }
; fold (urem x, pow2) -> (and x, pow2-1) ; fold (urem x, pow2) -> (and x, pow2-1)
define <vscale x 2 x i64> @vremu_vi_nxv2i64_1(<vscale x 2 x i64> %va) { define <vscale x 2 x i64> @vremu_vi_nxv2i64_1(<vscale x 2 x i64> %va) {
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; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0 %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%vc = urem <vscale x 4 x i64> %va, %splat %vc = urem <vscale x 4 x i64> %va, %splat
ret <vscale x 4 x i64> %vc ret <vscale x 4 x i64> %vc
} }
define <vscale x 4 x i64> @vremu_vi_nxv4i64_0(<vscale x 4 x i64> %va) { define <vscale x 4 x i64> @vremu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
; RV32-LABEL: vremu_vi_nxv4i64_0: ; RV32-V-LABEL: vremu_vi_nxv4i64_0:
; RV32: # %bb.0: ; RV32-V: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: lui a0, 131072 ; RV32-V-NEXT: lui a0, 131072
; RV32-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: sw a0, 12(sp)
; RV32-NEXT: li a0, 1 ; RV32-V-NEXT: li a0, 1
; RV32-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; RV32-V-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-V-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmulhu.vv v12, v8, v12 ; RV32-V-NEXT: vmulhu.vv v12, v8, v12
; RV32-NEXT: li a0, 61 ; RV32-V-NEXT: li a0, 61
; RV32-NEXT: vsrl.vx v12, v12, a0 ; RV32-V-NEXT: vsrl.vx v12, v12, a0
; RV32-NEXT: li a0, -7 ; RV32-V-NEXT: li a0, -7
; RV32-NEXT: vnmsac.vx v8, a0, v12 ; RV32-V-NEXT: vnmsac.vx v8, a0, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-V-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-V-NEXT: ret
; ;
; RV64-LABEL: vremu_vi_nxv4i64_0: ; ZVE64X-LABEL: vremu_vi_nxv4i64_0:
; RV64: # %bb.0: ; ZVE64X: # %bb.0:
; RV64-NEXT: li a0, 1 ; ZVE64X-NEXT: li a0, -7
; RV64-NEXT: slli a0, a0, 61 ; ZVE64X-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV64-NEXT: addi a0, a0, 1 ; ZVE64X-NEXT: vremu.vx v8, v8, a0
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; ZVE64X-NEXT: ret
; RV64-NEXT: vmulhu.vx v12, v8, a0 ;
; RV64-NEXT: li a0, 61 ; RV64-V-LABEL: vremu_vi_nxv4i64_0:
; RV64-NEXT: vsrl.vx v12, v12, a0 ; RV64-V: # %bb.0:
; RV64-NEXT: li a0, -7 ; RV64-V-NEXT: li a0, 1
; RV64-NEXT: vnmsac.vx v8, a0, v12 ; RV64-V-NEXT: slli a0, a0, 61
; RV64-NEXT: ret ; RV64-V-NEXT: addi a0, a0, 1
; RV64-V-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV64-V-NEXT: vmulhu.vx v12, v8, a0
; RV64-V-NEXT: li a0, 61
; RV64-V-NEXT: vsrl.vx v12, v12, a0
; RV64-V-NEXT: li a0, -7
; RV64-V-NEXT: vnmsac.vx v8, a0, v12
; RV64-V-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0 %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%vc = urem <vscale x 4 x i64> %va, %splat %vc = urem <vscale x 4 x i64> %va, %splat
ret <vscale x 4 x i64> %vc ret <vscale x 4 x i64> %vc
} }
; fold (urem x, pow2) -> (and x, pow2-1) ; fold (urem x, pow2) -> (and x, pow2-1)
define <vscale x 4 x i64> @vremu_vi_nxv4i64_1(<vscale x 4 x i64> %va) { define <vscale x 4 x i64> @vremu_vi_nxv4i64_1(<vscale x 4 x i64> %va) {
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; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = urem <vscale x 8 x i64> %va, %splat %vc = urem <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i64> %vc ret <vscale x 8 x i64> %vc
} }
define <vscale x 8 x i64> @vremu_vi_nxv8i64_0(<vscale x 8 x i64> %va) { define <vscale x 8 x i64> @vremu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
; RV32-LABEL: vremu_vi_nxv8i64_0: ; RV32-V-LABEL: vremu_vi_nxv8i64_0:
; RV32: # %bb.0: ; RV32-V: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: lui a0, 131072 ; RV32-V-NEXT: lui a0, 131072
; RV32-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: sw a0, 12(sp)
; RV32-NEXT: li a0, 1 ; RV32-V-NEXT: li a0, 1
; RV32-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; RV32-V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-V-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmulhu.vv v16, v8, v16 ; RV32-V-NEXT: vmulhu.vv v16, v8, v16
; RV32-NEXT: li a0, 61 ; RV32-V-NEXT: li a0, 61
; RV32-NEXT: vsrl.vx v16, v16, a0 ; RV32-V-NEXT: vsrl.vx v16, v16, a0
; RV32-NEXT: li a0, -7 ; RV32-V-NEXT: li a0, -7
; RV32-NEXT: vnmsac.vx v8, a0, v16 ; RV32-V-NEXT: vnmsac.vx v8, a0, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-V-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-V-NEXT: ret
; ;
; RV64-LABEL: vremu_vi_nxv8i64_0: ; ZVE64X-LABEL: vremu_vi_nxv8i64_0:
; RV64: # %bb.0: ; ZVE64X: # %bb.0:
; RV64-NEXT: li a0, 1 ; ZVE64X-NEXT: li a0, -7
; RV64-NEXT: slli a0, a0, 61 ; ZVE64X-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: addi a0, a0, 1 ; ZVE64X-NEXT: vremu.vx v8, v8, a0
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; ZVE64X-NEXT: ret
; RV64-NEXT: vmulhu.vx v16, v8, a0 ;
; RV64-NEXT: li a0, 61 ; RV64-V-LABEL: vremu_vi_nxv8i64_0:
; RV64-NEXT: vsrl.vx v16, v16, a0 ; RV64-V: # %bb.0:
; RV64-NEXT: li a0, -7 ; RV64-V-NEXT: li a0, 1
; RV64-NEXT: vnmsac.vx v8, a0, v16 ; RV64-V-NEXT: slli a0, a0, 61
; RV64-NEXT: ret ; RV64-V-NEXT: addi a0, a0, 1
; RV64-V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-V-NEXT: vmulhu.vx v16, v8, a0
; RV64-V-NEXT: li a0, 61
; RV64-V-NEXT: vsrl.vx v16, v16, a0
; RV64-V-NEXT: li a0, -7
; RV64-V-NEXT: vnmsac.vx v8, a0, v16
; RV64-V-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = urem <vscale x 8 x i64> %va, %splat %vc = urem <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i64> %vc ret <vscale x 8 x i64> %vc
} }
; fold (urem x, pow2) -> (and x, pow2-1) ; fold (urem x, pow2) -> (and x, pow2-1)
define <vscale x 8 x i64> @vremu_vi_nxv8i64_1(<vscale x 8 x i64> %va) { define <vscale x 8 x i64> @vremu_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
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