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Differential D117969 Diff 402261 llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll

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llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: -target-abi=ilp32d < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x float> @intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x float> @intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16: ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
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declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16( declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16(
<vscale x 1 x float>, <vscale x 1 x float>,
half, half,
i32); i32);
define <vscale x 1 x float> @intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16(<vscale x 1 x float> %0, half %1, i32 %2) nounwind { define <vscale x 1 x float> @intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16(<vscale x 1 x float> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v8, fa0
; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16( %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
half %1, half %1,
i32 %2) i32 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.mask.nxv1f32.f16( declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.mask.nxv1f32.f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
half, half,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32, i32,
i32); i32);
define <vscale x 1 x float> @intrinsic_vfwsub.w_mask_wf_nxv1f32_nxv1f32_f16(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x float> @intrinsic_vfwsub.w_mask_wf_nxv1f32_nxv1f32_f16(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv1f32_nxv1f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv1f32_nxv1f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v9, fa0, v0.t
; CHECK-NEXT: vfwsub.wf v8, v9, ft0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.mask.nxv1f32.f16( %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.mask.nxv1f32.f16(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
half %2, half %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16( declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16(
<vscale x 2 x float>, <vscale x 2 x float>,
half, half,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16(<vscale x 2 x float> %0, half %1, i32 %2) nounwind { define <vscale x 2 x float> @intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16(<vscale x 2 x float> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v8, fa0
; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
half %1, half %1,
i32 %2) i32 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.mask.nxv2f32.f16( declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.mask.nxv2f32.f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
half, half,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32, i32,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwsub.w_mask_wf_nxv2f32_nxv2f32_f16(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwsub.w_mask_wf_nxv2f32_nxv2f32_f16(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv2f32_nxv2f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv2f32_nxv2f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v9, fa0, v0.t
; CHECK-NEXT: vfwsub.wf v8, v9, ft0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.mask.nxv2f32.f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.mask.nxv2f32.f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
half %2, half %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f32.f16( declare <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f32.f16(
<vscale x 4 x float>, <vscale x 4 x float>,
half, half,
i32); i32);
define <vscale x 4 x float> @intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16(<vscale x 4 x float> %0, half %1, i32 %2) nounwind { define <vscale x 4 x float> @intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16(<vscale x 4 x float> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v8, fa0
; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f32.f16( %a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f32.f16(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
half %1, half %1,
i32 %2) i32 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwsub.w.mask.nxv4f32.f16( declare <vscale x 4 x float> @llvm.riscv.vfwsub.w.mask.nxv4f32.f16(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
half, half,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32, i32,
i32); i32);
define <vscale x 4 x float> @intrinsic_vfwsub.w_mask_wf_nxv4f32_nxv4f32_f16(<vscale x 4 x float> %0, <vscale x 4 x float> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x float> @intrinsic_vfwsub.w_mask_wf_nxv4f32_nxv4f32_f16(<vscale x 4 x float> %0, <vscale x 4 x float> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv4f32_nxv4f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv4f32_nxv4f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v10, fa0, v0.t
; CHECK-NEXT: vfwsub.wf v8, v10, ft0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.mask.nxv4f32.f16( %a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.mask.nxv4f32.f16(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
half %2, half %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f32.f16( declare <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f32.f16(
<vscale x 8 x float>, <vscale x 8 x float>,
half, half,
i32); i32);
define <vscale x 8 x float> @intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16(<vscale x 8 x float> %0, half %1, i32 %2) nounwind { define <vscale x 8 x float> @intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16(<vscale x 8 x float> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v8, fa0
; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f32.f16( %a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f32.f16(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
half %1, half %1,
i32 %2) i32 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwsub.w.mask.nxv8f32.f16( declare <vscale x 8 x float> @llvm.riscv.vfwsub.w.mask.nxv8f32.f16(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
half, half,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32, i32,
i32); i32);
define <vscale x 8 x float> @intrinsic_vfwsub.w_mask_wf_nxv8f32_nxv8f32_f16(<vscale x 8 x float> %0, <vscale x 8 x float> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x float> @intrinsic_vfwsub.w_mask_wf_nxv8f32_nxv8f32_f16(<vscale x 8 x float> %0, <vscale x 8 x float> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv8f32_nxv8f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv8f32_nxv8f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v12, fa0, v0.t
; CHECK-NEXT: vfwsub.wf v8, v12, ft0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.mask.nxv8f32.f16( %a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.mask.nxv8f32.f16(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
half %2, half %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.f16( declare <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.f16(
<vscale x 16 x float>, <vscale x 16 x float>,
half, half,
i32); i32);
define <vscale x 16 x float> @intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16(<vscale x 16 x float> %0, half %1, i32 %2) nounwind { define <vscale x 16 x float> @intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16(<vscale x 16 x float> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v8, fa0
; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.f16( %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.f16(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
half %1, half %1,
i32 %2) i32 %2)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.f16( declare <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.f16(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
half, half,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32, i32,
i32); i32);
define <vscale x 16 x float> @intrinsic_vfwsub.w_mask_wf_nxv16f32_nxv16f32_f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfwsub.w_mask_wf_nxv16f32_nxv16f32_f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv16f32_nxv16f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv16f32_nxv16f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v16, fa0, v0.t
; CHECK-NEXT: vfwsub.wf v8, v16, ft0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.f16( %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.f16(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
half %2, half %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwsub.w.nxv1f64.f32( declare <vscale x 1 x double> @llvm.riscv.vfwsub.w.nxv1f64.f32(
<vscale x 1 x double>, <vscale x 1 x double>,
float, float,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32(<vscale x 1 x double> %0, float %1, i32 %2) nounwind { define <vscale x 1 x double> @intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32(<vscale x 1 x double> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v8, fa0
; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.nxv1f64.f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.nxv1f64.f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
float %1, float %1,
i32 %2) i32 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwsub.w.mask.nxv1f64.f32( declare <vscale x 1 x double> @llvm.riscv.vfwsub.w.mask.nxv1f64.f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
float, float,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32, i32,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwsub.w_mask_wf_nxv1f64_nxv1f64_f32(<vscale x 1 x double> %0, <vscale x 1 x double> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwsub.w_mask_wf_nxv1f64_nxv1f64_f32(<vscale x 1 x double> %0, <vscale x 1 x double> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv1f64_nxv1f64_f32: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv1f64_nxv1f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v9, fa0, v0.t
; CHECK-NEXT: vfwsub.wf v8, v9, ft0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.mask.nxv1f64.f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.mask.nxv1f64.f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
float %2, float %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwsub.w.nxv2f64.f32( declare <vscale x 2 x double> @llvm.riscv.vfwsub.w.nxv2f64.f32(
<vscale x 2 x double>, <vscale x 2 x double>,
float, float,
i32); i32);
define <vscale x 2 x double> @intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32(<vscale x 2 x double> %0, float %1, i32 %2) nounwind { define <vscale x 2 x double> @intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32(<vscale x 2 x double> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v8, fa0
; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.nxv2f64.f32( %a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.nxv2f64.f32(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
float %1, float %1,
i32 %2) i32 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwsub.w.mask.nxv2f64.f32( declare <vscale x 2 x double> @llvm.riscv.vfwsub.w.mask.nxv2f64.f32(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
float, float,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32, i32,
i32); i32);
define <vscale x 2 x double> @intrinsic_vfwsub.w_mask_wf_nxv2f64_nxv2f64_f32(<vscale x 2 x double> %0, <vscale x 2 x double> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x double> @intrinsic_vfwsub.w_mask_wf_nxv2f64_nxv2f64_f32(<vscale x 2 x double> %0, <vscale x 2 x double> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv2f64_nxv2f64_f32: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv2f64_nxv2f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v10, fa0, v0.t
; CHECK-NEXT: vfwsub.wf v8, v10, ft0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.mask.nxv2f64.f32( %a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.mask.nxv2f64.f32(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
float %2, float %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwsub.w.nxv4f64.f32( declare <vscale x 4 x double> @llvm.riscv.vfwsub.w.nxv4f64.f32(
<vscale x 4 x double>, <vscale x 4 x double>,
float, float,
i32); i32);
define <vscale x 4 x double> @intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32(<vscale x 4 x double> %0, float %1, i32 %2) nounwind { define <vscale x 4 x double> @intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32(<vscale x 4 x double> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v8, fa0
; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.nxv4f64.f32( %a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.nxv4f64.f32(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
float %1, float %1,
i32 %2) i32 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwsub.w.mask.nxv4f64.f32( declare <vscale x 4 x double> @llvm.riscv.vfwsub.w.mask.nxv4f64.f32(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
float, float,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32, i32,
i32); i32);
define <vscale x 4 x double> @intrinsic_vfwsub.w_mask_wf_nxv4f64_nxv4f64_f32(<vscale x 4 x double> %0, <vscale x 4 x double> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x double> @intrinsic_vfwsub.w_mask_wf_nxv4f64_nxv4f64_f32(<vscale x 4 x double> %0, <vscale x 4 x double> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv4f64_nxv4f64_f32: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv4f64_nxv4f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v12, fa0, v0.t
; CHECK-NEXT: vfwsub.wf v8, v12, ft0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.mask.nxv4f64.f32( %a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.mask.nxv4f64.f32(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
float %2, float %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwsub.w.nxv8f64.f32( declare <vscale x 8 x double> @llvm.riscv.vfwsub.w.nxv8f64.f32(
<vscale x 8 x double>, <vscale x 8 x double>,
float, float,
i32); i32);
define <vscale x 8 x double> @intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32(<vscale x 8 x double> %0, float %1, i32 %2) nounwind { define <vscale x 8 x double> @intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32(<vscale x 8 x double> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v8, fa0
; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.nxv8f64.f32( %a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.nxv8f64.f32(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
float %1, float %1,
i32 %2) i32 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.f32( declare <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.f32(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
float, float,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32, i32,
i32); i32);
define <vscale x 8 x double> @intrinsic_vfwsub.w_mask_wf_nxv8f64_nxv8f64_f32(<vscale x 8 x double> %0, <vscale x 8 x double> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfwsub.w_mask_wf_nxv8f64_nxv8f64_f32(<vscale x 8 x double> %0, <vscale x 8 x double> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv8f64_nxv8f64_f32: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv8f64_nxv8f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v16, fa0, v0.t
; CHECK-NEXT: vfwsub.wf v8, v16, ft0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.f32( %a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.f32(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
float %2, float %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
▲ Show 20 Lines • Show All 152 Lines • ▼ Show 20 Lines %a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32(
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
define <vscale x 1 x float> @intrinsic_vfwsub.w_mask_wf_tie_nxv1f32_nxv1f32_f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x float> @intrinsic_vfwsub.w_mask_wf_tie_nxv1f32_nxv1f32_f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv1f32_nxv1f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv1f32_nxv1f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t
; CHECK-NEXT: vfwsub.wf v8, v8, ft0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.mask.nxv1f32.f16( %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.mask.nxv1f32.f16(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
half %1, half %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
define <vscale x 2 x float> @intrinsic_vfwsub.w_mask_wf_tie_nxv2f32_nxv2f32_f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwsub.w_mask_wf_tie_nxv2f32_nxv2f32_f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv2f32_nxv2f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv2f32_nxv2f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t
; CHECK-NEXT: vfwsub.wf v8, v8, ft0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.mask.nxv2f32.f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.mask.nxv2f32.f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
half %1, half %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
define <vscale x 4 x float> @intrinsic_vfwsub.w_mask_wf_tie_nxv4f32_nxv4f32_f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x float> @intrinsic_vfwsub.w_mask_wf_tie_nxv4f32_nxv4f32_f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv4f32_nxv4f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv4f32_nxv4f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t
; CHECK-NEXT: vfwsub.wf v8, v8, ft0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.mask.nxv4f32.f16( %a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.mask.nxv4f32.f16(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
half %1, half %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
define <vscale x 8 x float> @intrinsic_vfwsub.w_mask_wf_tie_nxv8f32_nxv8f32_f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x float> @intrinsic_vfwsub.w_mask_wf_tie_nxv8f32_nxv8f32_f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv8f32_nxv8f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv8f32_nxv8f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t
; CHECK-NEXT: vfwsub.wf v8, v8, ft0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.mask.nxv8f32.f16( %a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.mask.nxv8f32.f16(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
half %1, half %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
define <vscale x 16 x float> @intrinsic_vfwsub.w_mask_wf_tie_nxv16f32_nxv16f32_f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x float> @intrinsic_vfwsub.w_mask_wf_tie_nxv16f32_nxv16f32_f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv16f32_nxv16f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv16f32_nxv16f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t
; CHECK-NEXT: vfwsub.wf v8, v8, ft0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.f16( %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.f16(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
half %1, half %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
define <vscale x 1 x double> @intrinsic_vfwsub.w_mask_wf_tie_nxv1f64_nxv1f64_f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfwsub.w_mask_wf_tie_nxv1f64_nxv1f64_f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv1f64_nxv1f64_f32: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv1f64_nxv1f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t
; CHECK-NEXT: vfwsub.wf v8, v8, ft0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.mask.nxv1f64.f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.mask.nxv1f64.f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
float %1, float %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
define <vscale x 2 x double> @intrinsic_vfwsub.w_mask_wf_tie_nxv2f64_nxv2f64_f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x double> @intrinsic_vfwsub.w_mask_wf_tie_nxv2f64_nxv2f64_f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv2f64_nxv2f64_f32: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv2f64_nxv2f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t
; CHECK-NEXT: vfwsub.wf v8, v8, ft0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.mask.nxv2f64.f32( %a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.mask.nxv2f64.f32(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
float %1, float %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
define <vscale x 4 x double> @intrinsic_vfwsub.w_mask_wf_tie_nxv4f64_nxv4f64_f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x double> @intrinsic_vfwsub.w_mask_wf_tie_nxv4f64_nxv4f64_f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv4f64_nxv4f64_f32: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv4f64_nxv4f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t
; CHECK-NEXT: vfwsub.wf v8, v8, ft0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.mask.nxv4f64.f32( %a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.mask.nxv4f64.f32(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
float %1, float %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
define <vscale x 8 x double> @intrinsic_vfwsub.w_mask_wf_tie_nxv8f64_nxv8f64_f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x double> @intrinsic_vfwsub.w_mask_wf_tie_nxv8f64_nxv8f64_f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv8f64_nxv8f64_f32: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv8f64_nxv8f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t
; CHECK-NEXT: vfwsub.wf v8, v8, ft0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.f32( %a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.f32(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
float %1, float %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
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