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Differential D114703 Diff 393478 llvm/lib/Target/AArch64/AArch64TargetMachine.cpp

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llvm/lib/Target/AArch64/AArch64TargetMachine.cpp

Show First 20 Lines • Show All 111 Lines • ▼ Show 20 LinesEnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
cl::init(true)); cl::init(true));
static cl::opt<bool> static cl::opt<bool>
EnableCondOpt("aarch64-enable-condopt", EnableCondOpt("aarch64-enable-condopt",
cl::desc("Enable the condition optimizer pass"), cl::desc("Enable the condition optimizer pass"),
cl::init(true), cl::Hidden); cl::init(true), cl::Hidden);
static cl::opt<bool> static cl::opt<bool>
EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
cl::desc("Work around Cortex-A53 erratum 835769"),
cl::init(false));
static cl::opt<bool>
EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden, EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
cl::desc("Enable optimizations on complex GEPs"), cl::desc("Enable optimizations on complex GEPs"),
cl::init(false)); cl::init(false));
static cl::opt<bool> static cl::opt<bool>
BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true), BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
cl::desc("Relax out of range conditional branches")); cl::desc("Relax out of range conditional branches"));
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void AArch64PassConfig::addPreEmitPass() { void AArch64PassConfig::addPreEmitPass() {
// Machine Block Placement might have created new opportunities when run // Machine Block Placement might have created new opportunities when run
// at O3, where the Tail Duplication Threshold is set to 4 instructions. // at O3, where the Tail Duplication Threshold is set to 4 instructions.
// Run the load/store optimizer once more. // Run the load/store optimizer once more.
if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt) if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
addPass(createAArch64LoadStoreOptimizationPass()); addPass(createAArch64LoadStoreOptimizationPass());
if (EnableA53Fix835769)
addPass(createAArch64A53Fix835769()); addPass(createAArch64A53Fix835769());
if (EnableBranchTargets) if (EnableBranchTargets)
addPass(createAArch64BranchTargetsPass()); addPass(createAArch64BranchTargetsPass());
// Relax conditional branch instructions if they're otherwise out of // Relax conditional branch instructions if they're otherwise out of
// range of their destination. // range of their destination.
if (BranchRelaxation) if (BranchRelaxation)
addPass(&BranchRelaxationPassID); addPass(&BranchRelaxationPassID);
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