Changeset View
Changeset View
Standalone View
Standalone View
llvm/lib/Target/AArch64/AArch64.td
Show First 20 Lines • Show All 449 Lines • ▼ Show 20 Lines | def FeatureAppleA7SysReg : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true", | ||||
"Apple A7 (the CPU formerly known as Cyclone)">; | "Apple A7 (the CPU formerly known as Cyclone)">; | ||||
def FeatureEL2VMSA : SubtargetFeature<"el2vmsa", "HasEL2VMSA", "true", | def FeatureEL2VMSA : SubtargetFeature<"el2vmsa", "HasEL2VMSA", "true", | ||||
"Enable Exception Level 2 Virtual Memory System Architecture">; | "Enable Exception Level 2 Virtual Memory System Architecture">; | ||||
def FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true", | def FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true", | ||||
"Enable Exception Level 3">; | "Enable Exception Level 3">; | ||||
def FeatureFixCortexA53_835769 : SubtargetFeature<"fix-cortex-a53-835769", | |||||
"FixCortexA53_835769", "true", "Mitigate Cortex-A53 Erratum 835769">; | |||||
//===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
// Architectures. | // Architectures. | ||||
// | // | ||||
def HasV8_0aOps : SubtargetFeature<"v8a", "HasV8_0aOps", "true", | def HasV8_0aOps : SubtargetFeature<"v8a", "HasV8_0aOps", "true", | ||||
"Support ARM v8.0a instructions", [FeatureEL2VMSA, FeatureEL3]>; | "Support ARM v8.0a instructions", [FeatureEL2VMSA, FeatureEL3]>; | ||||
def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", | def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", | ||||
"Support ARM v8.1a instructions", [HasV8_0aOps, FeatureCRC, FeatureLSE, | "Support ARM v8.1a instructions", [HasV8_0aOps, FeatureCRC, FeatureLSE, | ||||
▲ Show 20 Lines • Show All 746 Lines • Show Last 20 Lines |