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Differential D112429 Diff 392315 llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

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llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

Show First 20 Lines • Show All 2,154 Lines • ▼ Show 20 Lines case ARM::TCRETURNri: {
if (MI.isCandidateForCallSiteEntry()) if (MI.isCandidateForCallSiteEntry())
MI.getMF()->moveCallSiteInfo(&MI, &*NewMI); MI.getMF()->moveCallSiteInfo(&MI, &*NewMI);
MBB.erase(MBBI); MBB.erase(MBBI);
MBBI = NewMI; MBBI = NewMI;
return true; return true;
} }
case ARM::tBXNS_RET: { case ARM::tBXNS_RET: {
// For v8.0-M.Main we need to authenticate LR before clearing FPRs, which
// uses R12 as a scratch register.
if (!STI->hasV8_1MMainlineOps() && AFI->shouldSignReturnAddress())
BuildMI(MBB, MBBI, DebugLoc(), TII->get(ARM::t2AUT));
MachineBasicBlock &AfterBB = CMSEClearFPRegs(MBB, MBBI); MachineBasicBlock &AfterBB = CMSEClearFPRegs(MBB, MBBI);
if (STI->hasV8_1MMainlineOps()) { if (STI->hasV8_1MMainlineOps()) {
// Restore the non-secure floating point context. // Restore the non-secure floating point context.
BuildMI(MBB, MBBI, MBBI->getDebugLoc(), BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
TII->get(ARM::VLDR_FPCXTNS_post), ARM::SP) TII->get(ARM::VLDR_FPCXTNS_post), ARM::SP)
.addReg(ARM::SP) .addReg(ARM::SP)
.addImm(4) .addImm(4)
.add(predOps(ARMCC::AL)); .add(predOps(ARMCC::AL));
if (AFI->shouldSignReturnAddress())
BuildMI(AfterBB, AfterBB.end(), DebugLoc(), TII->get(ARM::t2AUT));
} }
// Clear all GPR that are not a use of the return instruction. // Clear all GPR that are not a use of the return instruction.
assert(llvm::all_of(MBBI->operands(), [](const MachineOperand &Op) { assert(llvm::all_of(MBBI->operands(), [](const MachineOperand &Op) {
return !Op.isReg() || Op.getReg() != ARM::R12; return !Op.isReg() || Op.getReg() != ARM::R12;
})); }));
SmallVector<unsigned, 5> ClearRegs; SmallVector<unsigned, 5> ClearRegs;
determineGPRegsToClear( determineGPRegsToClear(
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