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llvm/lib/Target/ARM/ARMAsmPrinter.cpp
| Show First 20 Lines • Show All 1,147 Lines • ▼ Show 20 Lines | if (MI->mayStore()) { | ||||||||
| assert(DstReg == ARM::SP && | assert(DstReg == ARM::SP && | ||||||||
| "Only stack pointer as a destination reg is supported"); | "Only stack pointer as a destination reg is supported"); | ||||||||
| SmallVector<unsigned, 4> RegList; | SmallVector<unsigned, 4> RegList; | ||||||||
| // Skip src & dst reg, and pred ops. | // Skip src & dst reg, and pred ops. | ||||||||
| unsigned StartOp = 2 + 2; | unsigned StartOp = 2 + 2; | ||||||||
| // Use all the operands. | // Use all the operands. | ||||||||
| unsigned NumOffset = 0; | unsigned NumOffset = 0; | ||||||||
| // Amount of SP adjustment folded into a push. | // Amount of SP adjustment folded into a push, before the | ||||||||
| unsigned Pad = 0; | // registers are stored (pad at higher addresses). | ||||||||
danielkiss: NIT | |||||||||
| unsigned PadBefore = 0; | |||||||||
| // Amount of SP adjustment folded into a push, after the | |||||||||
| // registers are stored (pad at lower addresses). | |||||||||
danielkiss: | |||||||||
| unsigned PadAfter = 0; | |||||||||
| switch (Opc) { | switch (Opc) { | ||||||||
| default: | default: | ||||||||
| MI->print(errs()); | MI->print(errs()); | ||||||||
| llvm_unreachable("Unsupported opcode for unwinding information"); | llvm_unreachable("Unsupported opcode for unwinding information"); | ||||||||
| case ARM::tPUSH: | case ARM::tPUSH: | ||||||||
| // Special case here: no src & dst reg, but two extra imp ops. | // Special case here: no src & dst reg, but two extra imp ops. | ||||||||
| StartOp = 2; NumOffset = 2; | StartOp = 2; NumOffset = 2; | ||||||||
| Show All 14 Lines | case ARM::VSTMDDB_UPD: | ||||||||
| // push instruction are marked as undef and should not be | // push instruction are marked as undef and should not be | ||||||||
| // restored when unwinding, because the function can modify the | // restored when unwinding, because the function can modify the | ||||||||
| // corresponding stack slots. | // corresponding stack slots. | ||||||||
| if (MO.isUndef()) { | if (MO.isUndef()) { | ||||||||
| assert(RegList.empty() && | assert(RegList.empty() && | ||||||||
| "Pad registers must come before restored ones"); | "Pad registers must come before restored ones"); | ||||||||
| unsigned Width = | unsigned Width = | ||||||||
| TargetRegInfo->getRegSizeInBits(MO.getReg(), MachineRegInfo) / 8; | TargetRegInfo->getRegSizeInBits(MO.getReg(), MachineRegInfo) / 8; | ||||||||
| Pad += Width; | PadAfter += Width; | ||||||||
| continue; | continue; | ||||||||
| } | } | ||||||||
| // Check for registers that are remapped (for a Thumb1 prologue that | // Check for registers that are remapped (for a Thumb1 prologue that | ||||||||
| // saves high registers). | // saves high registers). | ||||||||
| Register Reg = MO.getReg(); | Register Reg = MO.getReg(); | ||||||||
| if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Reg)) | if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Reg)) | ||||||||
| Reg = RemappedReg; | Reg = RemappedReg; | ||||||||
| RegList.push_back(Reg); | RegList.push_back(Reg); | ||||||||
| } | } | ||||||||
| break; | break; | ||||||||
| case ARM::STR_PRE_IMM: | case ARM::STR_PRE_IMM: | ||||||||
| case ARM::STR_PRE_REG: | case ARM::STR_PRE_REG: | ||||||||
| case ARM::t2STR_PRE: | case ARM::t2STR_PRE: | ||||||||
| assert(MI->getOperand(2).getReg() == ARM::SP && | assert(MI->getOperand(2).getReg() == ARM::SP && | ||||||||
| "Only stack pointer as a source reg is supported"); | "Only stack pointer as a source reg is supported"); | ||||||||
| if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(SrcReg)) | |||||||||
| SrcReg = RemappedReg; | |||||||||
| RegList.push_back(SrcReg); | RegList.push_back(SrcReg); | ||||||||
| break; | break; | ||||||||
| case ARM::t2STRD_PRE: | |||||||||
| assert(MI->getOperand(3).getReg() == ARM::SP && | |||||||||
| "Only stack pointer as a source reg is supported"); | |||||||||
| SrcReg = MI->getOperand(1).getReg(); | |||||||||
| if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(SrcReg)) | |||||||||
| SrcReg = RemappedReg; | |||||||||
| RegList.push_back(SrcReg); | |||||||||
| SrcReg = MI->getOperand(2).getReg(); | |||||||||
| if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(SrcReg)) | |||||||||
| SrcReg = RemappedReg; | |||||||||
| RegList.push_back(SrcReg); | |||||||||
| PadBefore = -MI->getOperand(4).getImm() - 8; | |||||||||
| break; | |||||||||
| } | } | ||||||||
| if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) { | if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) { | ||||||||
| if (PadBefore) | |||||||||
| ATS.emitPad(PadBefore); | |||||||||
| ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD); | ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD); | ||||||||
| // Account for the SP adjustment, folded into the push. | // Account for the SP adjustment, folded into the push. | ||||||||
| if (Pad) | if (PadAfter) | ||||||||
| ATS.emitPad(Pad); | ATS.emitPad(PadAfter); | ||||||||
| } | } | ||||||||
| } else { | } else { | ||||||||
| // Changes of stack / frame pointer. | // Changes of stack / frame pointer. | ||||||||
| if (SrcReg == ARM::SP) { | if (SrcReg == ARM::SP) { | ||||||||
| int64_t Offset = 0; | int64_t Offset = 0; | ||||||||
| switch (Opc) { | switch (Opc) { | ||||||||
| default: | default: | ||||||||
| MI->print(errs()); | MI->print(errs()); | ||||||||
| ▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines | if (SrcReg == ARM::SP) { | ||||||||
| case ARM::t2MOVi16: | case ARM::t2MOVi16: | ||||||||
| Offset = MI->getOperand(1).getImm(); | Offset = MI->getOperand(1).getImm(); | ||||||||
| AFI->EHPrologueOffsetInRegs[DstReg] = Offset; | AFI->EHPrologueOffsetInRegs[DstReg] = Offset; | ||||||||
| break; | break; | ||||||||
| case ARM::t2MOVTi16: | case ARM::t2MOVTi16: | ||||||||
| Offset = MI->getOperand(2).getImm(); | Offset = MI->getOperand(2).getImm(); | ||||||||
| AFI->EHPrologueOffsetInRegs[DstReg] |= (Offset << 16); | AFI->EHPrologueOffsetInRegs[DstReg] |= (Offset << 16); | ||||||||
| break; | break; | ||||||||
| case ARM::t2PAC: | |||||||||
| case ARM::t2PACBTI: | |||||||||
| AFI->EHPrologueRemappedRegs[ARM::R12] = ARM::RA_AUTH_CODE; | |||||||||
| break; | |||||||||
| default: | default: | ||||||||
| MI->print(errs()); | MI->print(errs()); | ||||||||
| llvm_unreachable("Unsupported opcode for unwinding information"); | llvm_unreachable("Unsupported opcode for unwinding information"); | ||||||||
| } | } | ||||||||
| } | } | ||||||||
| } | } | ||||||||
| } | } | ||||||||
| ▲ Show 20 Lines • Show All 961 Lines • Show Last 20 Lines | |||||||||
NIT