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Differential D114174 Diff 388438 llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

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llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

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Show First 20 Lines • Show All 1,974 Lines • ▼ Show 20 Lines case AArch64ISD::FIRST_NUMBER:
MAKE_CASE(AArch64ISD::SBCS) MAKE_CASE(AArch64ISD::SBCS)
MAKE_CASE(AArch64ISD::ANDS) MAKE_CASE(AArch64ISD::ANDS)
MAKE_CASE(AArch64ISD::CCMP) MAKE_CASE(AArch64ISD::CCMP)
MAKE_CASE(AArch64ISD::CCMN) MAKE_CASE(AArch64ISD::CCMN)
MAKE_CASE(AArch64ISD::FCCMP) MAKE_CASE(AArch64ISD::FCCMP)
MAKE_CASE(AArch64ISD::FCMP) MAKE_CASE(AArch64ISD::FCMP)
MAKE_CASE(AArch64ISD::STRICT_FCMP) MAKE_CASE(AArch64ISD::STRICT_FCMP)
MAKE_CASE(AArch64ISD::STRICT_FCMPE) MAKE_CASE(AArch64ISD::STRICT_FCMPE)
MAKE_CASE(AArch64ISD::FCADD)
MAKE_CASE(AArch64ISD::DUP) MAKE_CASE(AArch64ISD::DUP)
MAKE_CASE(AArch64ISD::DUPLANE8) MAKE_CASE(AArch64ISD::DUPLANE8)
MAKE_CASE(AArch64ISD::DUPLANE16) MAKE_CASE(AArch64ISD::DUPLANE16)
MAKE_CASE(AArch64ISD::DUPLANE32) MAKE_CASE(AArch64ISD::DUPLANE32)
MAKE_CASE(AArch64ISD::DUPLANE64) MAKE_CASE(AArch64ISD::DUPLANE64)
MAKE_CASE(AArch64ISD::MOVI) MAKE_CASE(AArch64ISD::MOVI)
MAKE_CASE(AArch64ISD::MOVIshift) MAKE_CASE(AArch64ISD::MOVIshift)
MAKE_CASE(AArch64ISD::MOVIedit) MAKE_CASE(AArch64ISD::MOVIedit)
▲ Show 20 Lines • Show All 15,635 Lines • ▼ Show 20 Lines case ISD::INSERT_SUBVECTOR:
return; return;
case ISD::INTRINSIC_WO_CHAIN: { case ISD::INTRINSIC_WO_CHAIN: {
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
assert((VT == MVT::i8 || VT == MVT::i16) && assert((VT == MVT::i8 || VT == MVT::i16) &&
"custom lowering for unexpected type"); "custom lowering for unexpected type");
ConstantSDNode *CN = cast<ConstantSDNode>(N->getOperand(0)); ConstantSDNode *CN = cast<ConstantSDNode>(N->getOperand(0));
Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue()); Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
dbgs() << "Trying to lower intrinsic with id " << IntID << "\n";
N->dump();
switch (IntID) { switch (IntID) {
default: default:
return; return;
case Intrinsic::aarch64_sve_clasta_n: { case Intrinsic::aarch64_sve_clasta_n: {
SDLoc DL(N); SDLoc DL(N);
auto Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, N->getOperand(2)); auto Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, N->getOperand(2));
auto V = DAG.getNode(AArch64ISD::CLASTA_N, DL, MVT::i32, auto V = DAG.getNode(AArch64ISD::CLASTA_N, DL, MVT::i32,
N->getOperand(1), Op2, N->getOperand(3)); N->getOperand(1), Op2, N->getOperand(3));
▲ Show 20 Lines • Show All 1,430 Lines • Show Last 20 Lines