Page MenuHomePhabricator
Differential D111497 Diff 378465 llvm/lib/Target/M68k/M68kISelLowering.cpp

Changeset View

Standalone View

View Options

llvm/lib/Target/M68k/M68kISelLowering.cpp

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 LinesM68kTargetLowering::M68kTargetLowering(const M68kTargetMachine &TM,
// FIXME It would be better to use a custom lowering // FIXME It would be better to use a custom lowering
for (auto OP : {ISD::SMULO, ISD::UMULO}) { for (auto OP : {ISD::SMULO, ISD::UMULO}) {
setOperationAction(OP, MVT::i8, Expand); setOperationAction(OP, MVT::i8, Expand);
setOperationAction(OP, MVT::i16, Expand); setOperationAction(OP, MVT::i16, Expand);
setOperationAction(OP, MVT::i32, Expand); setOperationAction(OP, MVT::i32, Expand);
} }
for (auto OP : {ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS}) {
myhsuUnsubmitted
Not Done
ReplyInline Actions

Please remove curly brace if there is only one statement in for-loop.

myhsu: Please remove curly brace if there is only one statement in for-loop.
setOperationAction(OP, MVT::i32, Expand);
}
// Add/Sub overflow ops with MVT::Glues are lowered to CCR dependences. // Add/Sub overflow ops with MVT::Glues are lowered to CCR dependences.
for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) { for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
setOperationAction(ISD::ADDC, VT, Custom); setOperationAction(ISD::ADDC, VT, Custom);
setOperationAction(ISD::ADDE, VT, Custom); setOperationAction(ISD::ADDE, VT, Custom);
setOperationAction(ISD::SUBC, VT, Custom); setOperationAction(ISD::SUBC, VT, Custom);
setOperationAction(ISD::SUBE, VT, Custom); setOperationAction(ISD::SUBE, VT, Custom);
} }
▲ Show 20 Lines • Show All 262 Lines • ▼ Show 20 Lines
} }
SDValue SDValue
M68kTargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv, M68kTargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
const SDLoc &DL, SelectionDAG &DAG, const SDLoc &DL, SelectionDAG &DAG,
const CCValAssign &VA, const CCValAssign &VA,
MachineFrameInfo &MFI, MachineFrameInfo &MFI,
unsigned ArgIdx) const { unsigned ArgIdx) const {
myhsuUnsubmitted
Not Done
ReplyInline Actions

I feel like this is modified by clang-format. Can you format only the part you changed using clang/tools/clang-format/clang-format-diff.py

myhsu: I feel like this is modified by clang-format. Can you format //only// the part you changed…
// Create the nodes corresponding to a load from this parameter slot. // Create the nodes corresponding to a load from this parameter slot.
ISD::ArgFlagsTy Flags = Ins[ArgIdx].Flags; ISD::ArgFlagsTy Flags = Ins[ArgIdx].Flags;
EVT ValVT; EVT ValVT;
// If value is passed by pointer we have address passed instead of the value // If value is passed by pointer we have address passed instead of the value
// itself. // itself.
if (VA.getLocInfo() == CCValAssign::Indirect) if (VA.getLocInfo() == CCValAssign::Indirect)
ValVT = VA.getLocVT(); ValVT = VA.getLocVT();
▲ Show 20 Lines • Show All 919 Lines • ▼ Show 20 Linesbool M68kTargetLowering::IsEligibleForTailCallOptimization(
return true; return true;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Custom Lower // Custom Lower
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
SDValue M68kTargetLowering::LowerOperation(SDValue Op, SDValue M68kTargetLowering::LowerOperation(SDValue Op,
jrtc27Unsubmitted
Not Done
ReplyInline Actions

Keep order in this file consistent with the header

jrtc27: Keep order in this file consistent with the header
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
switch (Op.getOpcode()) { switch (Op.getOpcode()) {
default: default:
llvm_unreachable("Should not custom lower this!"); llvm_unreachable("Should not custom lower this!");
case ISD::SADDO: case ISD::SADDO:
case ISD::UADDO: case ISD::UADDO:
case ISD::SSUBO: case ISD::SSUBO:
case ISD::USUBO: case ISD::USUBO:
jrtc27Unsubmitted
Not Done
ReplyInline Actions

XLEN is a RISC-V-specific term, referring to the size of its X registers

jrtc27: XLEN is a RISC-V-specific term, referring to the size of its X registers
AnnikaCodesUnsubmitted
Done
ReplyInline Actions

Oh, sorry; I didn't know that.

AnnikaCodes: Oh, sorry; I didn't know that.
case ISD::SMULO: case ISD::SMULO:
case ISD::UMULO: case ISD::UMULO:
return LowerXALUO(Op, DAG); return LowerXALUO(Op, DAG);
case ISD::SETCC: case ISD::SETCC:
return LowerSETCC(Op, DAG); return LowerSETCC(Op, DAG);
case ISD::SETCCCARRY: case ISD::SETCCCARRY:
return LowerSETCCCARRY(Op, DAG); return LowerSETCCCARRY(Op, DAG);
case ISD::SELECT: case ISD::SELECT:
▲ Show 20 Lines • Show All 1,909 Lines • ▼ Show 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
static SDValue getSETCC(M68k::CondCode Cond, SDValue CCR, const SDLoc &dl, static SDValue getSETCC(M68k::CondCode Cond, SDValue CCR, const SDLoc &dl,
SelectionDAG &DAG) { SelectionDAG &DAG) {
return DAG.getNode(M68kISD::SETCC, dl, MVT::i8, return DAG.getNode(M68kISD::SETCC, dl, MVT::i8,
DAG.getConstant(Cond, dl, MVT::i8), CCR); DAG.getConstant(Cond, dl, MVT::i8), CCR);
} }
// When legalizing carry, we create carries via add X, -1 // When legalizing carry, we create carries via add X, -1
// If that comes from an actual carry, via setcc, we use the // If that comes from an actual carry, via setcc, we use the
craig.topperUnsubmitted
Done
ReplyInline Actions

"register size - ShAmt" -> "register size - 1 - ShAmt" right?

craig.topper: "register size - ShAmt" -> "register size - 1 - ShAmt" right?
// carry directly. // carry directly.
static SDValue combineCarryThroughADD(SDValue CCR) { static SDValue combineCarryThroughADD(SDValue CCR) {
if (CCR.getOpcode() == M68kISD::ADD) { if (CCR.getOpcode() == M68kISD::ADD) {
if (isAllOnesConstant(CCR.getOperand(1))) { if (isAllOnesConstant(CCR.getOperand(1))) {
SDValue Carry = CCR.getOperand(0); SDValue Carry = CCR.getOperand(0);
while (Carry.getOpcode() == ISD::TRUNCATE || while (Carry.getOpcode() == ISD::TRUNCATE ||
Carry.getOpcode() == ISD::ZERO_EXTEND || Carry.getOpcode() == ISD::ZERO_EXTEND ||
Carry.getOpcode() == ISD::SIGN_EXTEND || Carry.getOpcode() == ISD::SIGN_EXTEND ||
Carry.getOpcode() == ISD::ANY_EXTEND || Carry.getOpcode() == ISD::ANY_EXTEND ||
(Carry.getOpcode() == ISD::AND && (Carry.getOpcode() == ISD::AND &&
isOneConstant(Carry.getOperand(1)))) isOneConstant(Carry.getOperand(1))))
AnnikaCodesUnsubmitted
Done
ReplyInline Actions

These other changes are because I ran clang-format on the file; it's syntactically the same.

AnnikaCodes: These other changes are because I ran `clang-format` on the file; it's syntactically the same.
myhsuUnsubmitted
Not Done
ReplyInline Actions

ditto, please use clang-format-diff.py instead

myhsu: ditto, please use clang-format-diff.py instead
craig.topperUnsubmitted
Done
ReplyInline Actions

This sub can be an xor. See D119411

I don't m68k, does it have an xor with immediate instruction?

craig.topper: This sub can be an xor. See D119411 I don't m68k, does it have an xor with immediate…
Carry = Carry.getOperand(0); Carry = Carry.getOperand(0);
if (Carry.getOpcode() == M68kISD::SETCC || if (Carry.getOpcode() == M68kISD::SETCC ||
Carry.getOpcode() == M68kISD::SETCC_CARRY) { Carry.getOpcode() == M68kISD::SETCC_CARRY) {
if (Carry.getConstantOperandVal(0) == M68k::COND_CS) if (Carry.getConstantOperandVal(0) == M68k::COND_CS)
return Carry.getOperand(1); return Carry.getOperand(1);
} }
} }
} }
return SDValue(); return SDValue();
} }
0x59616eAuthorUnsubmitted
Not Done
ReplyInline Actions
SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusRegisterSize);
- SDValue CC =
- DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);
+ SDValue CC =
+ DAG.getSetCC(DL, MVT::i8, Shamt, DAG.getConstant(32, DL, VT), ISD::SETLT);
Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero);

That error seems result from here.

0x59616e: That error seems result from here.
/// Optimize a CCR definition used according to the condition code \p CC into /// Optimize a CCR definition used according to the condition code \p CC into
/// a simpler CCR value, potentially returning a new \p CC and replacing uses /// a simpler CCR value, potentially returning a new \p CC and replacing uses
/// of chain values. /// of chain values.
static SDValue combineSetCCCCR(SDValue CCR, M68k::CondCode &CC, static SDValue combineSetCCCCR(SDValue CCR, M68k::CondCode &CC,
SelectionDAG &DAG, SelectionDAG &DAG,
craig.topperUnsubmitted
Done
ReplyInline Actions

This temporary array is unnecessary. You can write

return DAG.getMergeValues({Lo, Hi}, DL);
craig.topper: This temporary array is unnecessary. You can write ``` return DAG.getMergeValues({Lo, Hi}, DL)…
const M68kSubtarget &Subtarget) { const M68kSubtarget &Subtarget) {
if (CC == M68k::COND_CS) if (CC == M68k::COND_CS)
if (SDValue Flags = combineCarryThroughADD(CCR)) if (SDValue Flags = combineCarryThroughADD(CCR))
return Flags; return Flags;
return SDValue(); return SDValue();
} }
// Optimize RES = M68kISD::SETCC CONDCODE, CCR_INPUT // Optimize RES = M68kISD::SETCC CONDCODE, CCR_INPUT
static SDValue combineM68kSetCC(SDNode *N, SelectionDAG &DAG, static SDValue combineM68kSetCC(SDNode *N, SelectionDAG &DAG,
const M68kSubtarget &Subtarget) { const M68kSubtarget &Subtarget) {
SDLoc DL(N); SDLoc DL(N);
M68k::CondCode CC = M68k::CondCode(N->getConstantOperandVal(0)); M68k::CondCode CC = M68k::CondCode(N->getConstantOperandVal(0));
SDValue CCR = N->getOperand(1); SDValue CCR = N->getOperand(1);
// Try to simplify the CCR and condition code operands. // Try to simplify the CCR and condition code operands.
if (SDValue Flags = combineSetCCCCR(CCR, CC, DAG, Subtarget)) if (SDValue Flags = combineSetCCCCR(CCR, CC, DAG, Subtarget))
return getSETCC(CC, Flags, DL, DAG); return getSETCC(CC, Flags, DL, DAG);
return SDValue(); return SDValue();
} }
static SDValue combineM68kBrCond(SDNode *N, SelectionDAG &DAG, static SDValue combineM68kBrCond(SDNode *N, SelectionDAG &DAG,
const M68kSubtarget &Subtarget) { const M68kSubtarget &Subtarget) {
SDLoc DL(N); SDLoc DL(N);
M68k::CondCode CC = M68k::CondCode(N->getConstantOperandVal(2)); M68k::CondCode CC = M68k::CondCode(N->getConstantOperandVal(2));
myhsuUnsubmitted
Done
ReplyInline Actions

Appreciate the explanations here :-)

myhsu: Appreciate the explanations here :-)
SDValue CCR = N->getOperand(3); SDValue CCR = N->getOperand(3);
// Try to simplify the CCR and condition code operands. // Try to simplify the CCR and condition code operands.
// Make sure to not keep references to operands, as combineSetCCCCR can // Make sure to not keep references to operands, as combineSetCCCCR can
// RAUW them under us. // RAUW them under us.
if (SDValue Flags = combineSetCCCCR(CCR, CC, DAG, Subtarget)) { if (SDValue Flags = combineSetCCCCR(CCR, CC, DAG, Subtarget)) {
SDValue Cond = DAG.getConstant(CC, DL, MVT::i8); SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
return DAG.getNode(M68kISD::BRCOND, DL, N->getVTList(), N->getOperand(0), return DAG.getNode(M68kISD::BRCOND, DL, N->getVTList(), N->getOperand(0),
N->getOperand(1), Cond, Flags); N->getOperand(1), Cond, Flags);
} }
return SDValue(); return SDValue();
} }
static SDValue combineSUBX(SDNode *N, SelectionDAG &DAG) { static SDValue combineSUBX(SDNode *N, SelectionDAG &DAG) {
if (SDValue Flags = combineCarryThroughADD(N->getOperand(2))) { if (SDValue Flags = combineCarryThroughADD(N->getOperand(2))) {
MVT VT = N->getSimpleValueType(0); MVT VT = N->getSimpleValueType(0);
SDVTList VTs = DAG.getVTList(VT, MVT::i32); SDVTList VTs = DAG.getVTList(VT, MVT::i32);
return DAG.getNode(M68kISD::SUBX, SDLoc(N), VTs, N->getOperand(0), return DAG.getNode(M68kISD::SUBX, SDLoc(N), VTs, N->getOperand(0),
N->getOperand(1), Flags); N->getOperand(1), Flags);
} }
return SDValue(); return SDValue();
} }
// Optimize RES, CCR = M68kISD::ADDX LHS, RHS, CCR // Optimize RES, CCR = M68kISD::ADDX LHS, RHS, CCR
0x59616eAuthorUnsubmitted
Done
ReplyInline Actions
IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, RegisterSizeMinus1) : Zero;
- SDValue CC =
- DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);
-
+ SDValue CC =
+ DAG.getSetCC(DL, MVT::i8, Shamt, DAG.getConstant(32, DL, VT), ISD::SETLT);
Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse);

...and here.

0x59616e: ...and here.
static SDValue combineADDX(SDNode *N, SelectionDAG &DAG, static SDValue combineADDX(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI) { TargetLowering::DAGCombinerInfo &DCI) {
if (SDValue Flags = combineCarryThroughADD(N->getOperand(2))) { if (SDValue Flags = combineCarryThroughADD(N->getOperand(2))) {
MVT VT = N->getSimpleValueType(0); MVT VT = N->getSimpleValueType(0);
SDVTList VTs = DAG.getVTList(VT, MVT::i32); SDVTList VTs = DAG.getVTList(VT, MVT::i32);
return DAG.getNode(M68kISD::ADDX, SDLoc(N), VTs, N->getOperand(0), return DAG.getNode(M68kISD::ADDX, SDLoc(N), VTs, N->getOperand(0),
N->getOperand(1), Flags); N->getOperand(1), Flags);
} }
▲ Show 20 Lines • Show All 86 Lines • Show Last 20 Lines