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Differential D109379 Diff 372051 llvm/test/CodeGen/PowerPC/ldst-with-length-vector.ll

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llvm/test/CodeGen/PowerPC/ldst-with-length-vector.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
nemanjaiUnsubmitted
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This needs to have a big endian line as well and also a -O0 for each to ensure that it works with FastISEL.

nemanjai: This needs to have a big endian line as well and also a `-O0` for each to ensure that it works…
define void @store_vl_v2i64(<2 x i64>* %ptr, <2 x i64> %val, i32 %evl) {
; CHECK-LABEL: store_vl_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: sldi 4, 7, 59
; CHECK-NEXT: stxvl 34, 3, 4
nemanjaiUnsubmitted
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I must be missing something here. I thought the %evl parameter is the explicit vector length but it is clearly getting ignored and we are shifting a constant. So I don't really follow what is happening here.

nemanjai: I must be missing something here. I thought the `%evl` parameter is the `explicit vector…
; CHECK-NEXT: blr
call void @llvm.vp.store.v2i64(<2 x i64> %val, <2 x i64>* %ptr, <2 x i1> undef, i32 %evl)
ret void
}
declare void @llvm.vp.store.v2i64(<2 x i64>, <2 x i64>*, <2 x i1>, i32)
define <2 x i64> @load_vl_v2i64_i32(<2 x i64>* %ptr, i32 %evl) {
; CHECK-LABEL: load_vl_v2i64_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: sldi 4, 4, 59
; CHECK-NEXT: lxvl 34, 3, 4
; CHECK-NEXT: blr
%res = call <2 x i64> @llvm.vp.load.v2i64(<2 x i64>* %ptr, <2 x i1> undef, i32 %evl)
ret <2 x i64> %res
}
declare <2 x i64> @llvm.vp.load.v2i64(<2 x i64>*, <2 x i1>, i32)
define void @store_vl_v4i32(<4 x i32>* %ptr, <4 x i32> %val, i32 %evl) {
; CHECK-LABEL: store_vl_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: sldi 4, 7, 58
; CHECK-NEXT: stxvl 34, 3, 4
; CHECK-NEXT: blr
call void @llvm.vp.store.v4i32(<4 x i32> %val, <4 x i32>* %ptr, <4 x i1> undef, i32 %evl)
ret void
}
declare void @llvm.vp.store.v4i32(<4 x i32>, <4 x i32>*, <4 x i1>, i32)
define <4 x i32> @load_vl_v4i32_i32(<4 x i32>* %ptr, i32 %evl) {
; CHECK-LABEL: load_vl_v4i32_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: sldi 4, 4, 58
; CHECK-NEXT: lxvl 34, 3, 4
; CHECK-NEXT: blr
%res = call <4 x i32> @llvm.vp.load.v4i32(<4 x i32>* %ptr, <4 x i1> undef, i32 %evl)
ret <4 x i32> %res
}
declare <4 x i32> @llvm.vp.load.v4i32(<4 x i32>*, <4 x i1>, i32)
define void @store_vl_v8i16(<8 x i16>* %ptr, <8 x i16> %val, i32 %evl) {
; CHECK-LABEL: store_vl_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: sldi 4, 7, 57
; CHECK-NEXT: stxvl 34, 3, 4
; CHECK-NEXT: blr
call void @llvm.vp.store.v8i16(<8 x i16> %val, <8 x i16>* %ptr, <8 x i1> undef, i32 %evl)
ret void
}
declare void @llvm.vp.store.v8i16(<8 x i16>, <8 x i16>*, <8 x i1>, i32)
define <8 x i16> @load_vl_v8i16_i32(<8 x i16>* %ptr, i32 %evl) {
; CHECK-LABEL: load_vl_v8i16_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: sldi 4, 4, 57
; CHECK-NEXT: lxvl 34, 3, 4
; CHECK-NEXT: blr
%res = call <8 x i16> @llvm.vp.load.v8i16(<8 x i16>* %ptr, <8 x i1> undef, i32 %evl)
ret <8 x i16> %res
}
declare <8 x i16> @llvm.vp.load.v8i16(<8 x i16>*, <8 x i1>, i32)
define void @store_vl_v16i8(<16 x i8>* %ptr, <16 x i8> %val, i32 %evl) {
; CHECK-LABEL: store_vl_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: sldi 4, 7, 56
; CHECK-NEXT: stxvl 34, 3, 4
; CHECK-NEXT: blr
call void @llvm.vp.store.v16i8(<16 x i8> %val, <16 x i8>* %ptr, <16 x i1> undef, i32 %evl)
ret void
}
declare void @llvm.vp.store.v16i8(<16 x i8>, <16 x i8>*, <16 x i1>, i32)
define <16 x i8> @load_vl_v16i8_i32(<16 x i8>* %ptr, i32 %evl) {
; CHECK-LABEL: load_vl_v16i8_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: sldi 4, 4, 56
; CHECK-NEXT: lxvl 34, 3, 4
; CHECK-NEXT: blr
%res = call <16 x i8> @llvm.vp.load.v16i8(<16 x i8>* %ptr, <16 x i1> undef, i32 %evl)
ret <16 x i8> %res
}
declare <16 x i8> @llvm.vp.load.v16i8(<16 x i8>*, <16 x i1>, i32)
define void @store_vl_v4i64(<4 x i64>* %ptr, <4 x i64> %val, i32 %evl) {
; CHECK-LABEL: store_vl_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li 5, 1
; CHECK-NEXT: addi 4, 3, 16
; CHECK-NEXT: rldic 5, 5, 60, 3
; CHECK-NEXT: stxvl 35, 4, 5
; CHECK-NEXT: stxvl 34, 3, 5
; CHECK-NEXT: blr
call void @llvm.vp.store.v4i64(<4 x i64> %val, <4 x i64>* %ptr, <4 x i1> undef, i32 %evl)
ret void
}
declare void @llvm.vp.store.v4i64(<4 x i64>, <4 x i64>*, <4 x i1>, i32)
define <4 x i64> @load_vl_v4i64_i32(<4 x i64>* %ptr, i32 %evl) {
; CHECK-LABEL: load_vl_v4i64_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 1
; CHECK-NEXT: rldic 4, 4, 60, 3
; CHECK-NEXT: lxvl 34, 3, 4
; CHECK-NEXT: addi 3, 3, 16
; CHECK-NEXT: lxvl 35, 3, 4
; CHECK-NEXT: blr
%res = call <4 x i64> @llvm.vp.load.v4i64(<4 x i64>* %ptr, <4 x i1> undef, i32 %evl)
ret <4 x i64> %res
}
declare <4 x i64> @llvm.vp.load.v4i64(<4 x i64>*, <4 x i1>, i32)
define void @store_vl_v8i32(<8 x i32>* %ptr, <8 x i32> %val, i32 %evl) {
; CHECK-LABEL: store_vl_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li 5, 1
; CHECK-NEXT: addi 4, 3, 16
; CHECK-NEXT: rldic 5, 5, 60, 3
; CHECK-NEXT: stxvl 35, 4, 5
; CHECK-NEXT: stxvl 34, 3, 5
; CHECK-NEXT: blr
call void @llvm.vp.store.v8i32(<8 x i32> %val, <8 x i32>* %ptr, <8 x i1> undef, i32 %evl)
ret void
}
declare void @llvm.vp.store.v8i32(<8 x i32>, <8 x i32>*, <8 x i1>, i32)
define <8 x i32> @load_vl_v8i32_i32(<8 x i32>* %ptr, i32 %evl) {
; CHECK-LABEL: load_vl_v8i32_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 1
; CHECK-NEXT: rldic 4, 4, 60, 3
; CHECK-NEXT: lxvl 34, 3, 4
; CHECK-NEXT: addi 3, 3, 16
; CHECK-NEXT: lxvl 35, 3, 4
; CHECK-NEXT: blr
%res = call <8 x i32> @llvm.vp.load.v8i32(<8 x i32>* %ptr, <8 x i1> undef, i32 %evl)
ret <8 x i32> %res
}
declare <8 x i32> @llvm.vp.load.v8i32(<8 x i32>*, <8 x i1>, i32)
define void @store_vl_v16i16(<16 x i16>* %ptr, <16 x i16> %val, i32 %evl) {
; CHECK-LABEL: store_vl_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: li 5, 1
; CHECK-NEXT: addi 4, 3, 16
; CHECK-NEXT: rldic 5, 5, 60, 3
; CHECK-NEXT: stxvl 35, 4, 5
; CHECK-NEXT: stxvl 34, 3, 5
; CHECK-NEXT: blr
call void @llvm.vp.store.v16i16(<16 x i16> %val, <16 x i16>* %ptr, <16 x i1> undef, i32 %evl)
ret void
}
declare void @llvm.vp.store.v16i16(<16 x i16>, <16 x i16>*, <16 x i1>, i32)
define <16 x i16> @load_vl_v16i16_i32(<16 x i16>* %ptr, i32 %evl) {
; CHECK-LABEL: load_vl_v16i16_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 1
; CHECK-NEXT: rldic 4, 4, 60, 3
; CHECK-NEXT: lxvl 34, 3, 4
; CHECK-NEXT: addi 3, 3, 16
; CHECK-NEXT: lxvl 35, 3, 4
; CHECK-NEXT: blr
%res = call <16 x i16> @llvm.vp.load.v16i16(<16 x i16>* %ptr, <16 x i1> undef, i32 %evl)
ret <16 x i16> %res
}
declare <16 x i16> @llvm.vp.load.v16i16(<16 x i16>*, <16 x i1>, i32)
define void @store_vl_v32i8(<32 x i8>* %ptr, <32 x i8> %val, i32 %evl) {
; CHECK-LABEL: store_vl_v32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: li 5, 1
; CHECK-NEXT: addi 4, 3, 16
; CHECK-NEXT: rldic 5, 5, 60, 3
; CHECK-NEXT: stxvl 35, 4, 5
; CHECK-NEXT: stxvl 34, 3, 5
; CHECK-NEXT: blr
call void @llvm.vp.store.v32i8(<32 x i8> %val, <32 x i8>* %ptr, <32 x i1> undef, i32 %evl)
ret void
}
declare void @llvm.vp.store.v32i8(<32 x i8>, <32 x i8>*, <32 x i1>, i32)
define <32 x i8> @load_vl_v32i8_i32(<32 x i8>* %ptr, i32 %evl) {
; CHECK-LABEL: load_vl_v32i8_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 1
; CHECK-NEXT: rldic 4, 4, 60, 3
; CHECK-NEXT: lxvl 34, 3, 4
; CHECK-NEXT: addi 3, 3, 16
; CHECK-NEXT: lxvl 35, 3, 4
; CHECK-NEXT: blr
%res = call <32 x i8> @llvm.vp.load.v32i8(<32 x i8>* %ptr, <32 x i1> undef, i32 %evl)
ret <32 x i8> %res
}
declare <32 x i8> @llvm.vp.load.v32i8(<32 x i8>*, <32 x i1>, i32)
define void @store_vl_v3i64(<3 x i64>* %ptr, <3 x i64> %val, i32 %evl) {
; CHECK-LABEL: store_vl_v3i64:
; CHECK: # %bb.0:
; CHECK-NEXT: mtvsrdd 35, 5, 4
; CHECK-NEXT: li 4, 1
; CHECK-NEXT: mtfprd 0, 6
; CHECK-NEXT: xxswapd 34, 0
; CHECK-NEXT: rldic 5, 4, 60, 3
; CHECK-NEXT: rldic 4, 4, 59, 4
; CHECK-NEXT: stxvl 35, 3, 5
; CHECK-NEXT: addi 3, 3, 16
; CHECK-NEXT: stxvl 34, 3, 4
; CHECK-NEXT: blr
call void @llvm.vp.store.v3i64(<3 x i64> %val, <3 x i64>* %ptr, <3 x i1> undef, i32 %evl)
ret void
}
declare void @llvm.vp.store.v3i64(<3 x i64>, <3 x i64>*, <3 x i1>, i32)
define <3 x i64> @load_vl_v3i64_i32(<3 x i64>* %ptr, i32 %evl) {
; CHECK-LABEL: load_vl_v3i64_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li 5, 1
; CHECK-NEXT: addi 4, 3, 16
; CHECK-NEXT: rldic 6, 5, 59, 4
; CHECK-NEXT: lxvl 34, 4, 6
; CHECK-NEXT: rldic 4, 5, 60, 3
; CHECK-NEXT: lxvl 0, 3, 4
; CHECK-NEXT: mfvsrld 5, 34
; CHECK-NEXT: mfvsrld 3, 0
; CHECK-NEXT: mffprd 4, 0
; CHECK-NEXT: blr
%res = call <3 x i64> @llvm.vp.load.v3i64(<3 x i64>* %ptr, <3 x i1> undef, i32 %evl)
ret <3 x i64> %res
}
declare <3 x i64> @llvm.vp.load.v3i64(<3 x i64>*, <3 x i1>, i32)
define void @store_vl_v7i32(<7 x i32>* %ptr, <7 x i32> %val, i32 %evl) {
; CHECK-LABEL: store_vl_v7i32:
; CHECK: # %bb.0:
; CHECK-NEXT: rldimi 4, 5, 32, 0
; CHECK-NEXT: rldimi 6, 7, 32, 0
; CHECK-NEXT: mtvsrwz 34, 8
; CHECK-NEXT: mtvsrwz 35, 9
; CHECK-NEXT: mtvsrwz 36, 10
; CHECK-NEXT: mtvsrdd 0, 6, 4
; CHECK-NEXT: addis 4, 2, .LCPI18_0@toc@ha
; CHECK-NEXT: vmrghw 2, 3, 2
; CHECK-NEXT: addi 4, 4, .LCPI18_0@toc@l
; CHECK-NEXT: lxv 35, 0(4)
; CHECK-NEXT: li 4, 1
; CHECK-NEXT: rldic 4, 4, 60, 3
; CHECK-NEXT: stxvl 0, 3, 4
; CHECK-NEXT: li 4, 3
; CHECK-NEXT: addi 3, 3, 16
; CHECK-NEXT: vperm 2, 4, 2, 3
; CHECK-NEXT: rldic 4, 4, 58, 4
; CHECK-NEXT: stxvl 34, 3, 4
; CHECK-NEXT: blr
call void @llvm.vp.store.v7i32(<7 x i32> %val, <7 x i32>* %ptr, <7 x i1> undef, i32 %evl)
ret void
}
declare void @llvm.vp.store.v7i32(<7 x i32>, <7 x i32>*, <7 x i1>, i32)
define <7 x i32> @load_vl_v7i32_i32(<7 x i32>* %ptr, i32 %evl) {
; CHECK-LABEL: load_vl_v7i32_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li 5, 1
; CHECK-NEXT: rldic 5, 5, 60, 3
; CHECK-NEXT: lxvl 0, 4, 5
; CHECK-NEXT: li 5, 3
; CHECK-NEXT: addi 4, 4, 16
; CHECK-NEXT: rldic 5, 5, 58, 4
; CHECK-NEXT: lxvl 1, 4, 5
; CHECK-NEXT: li 4, 24
; CHECK-NEXT: stfiwx 1, 3, 4
; CHECK-NEXT: stxv 0, 0(3)
; CHECK-NEXT: xxswapd 0, 1
; CHECK-NEXT: stfd 0, 16(3)
; CHECK-NEXT: blr
%res = call <7 x i32> @llvm.vp.load.v7i32(<7 x i32>* %ptr, <7 x i1> undef, i32 %evl)
ret <7 x i32> %res
}
declare <7 x i32> @llvm.vp.load.v7i32(<7 x i32>*, <7 x i1>, i32)
define void @store_vl_v15i16(<15 x i16>* %ptr, <15 x i16> %val, i32 %evl) {
; CHECK-LABEL: store_vl_v15i16:
; CHECK: # %bb.0:
; CHECK-NEXT: mtvsrd 34, 4
; CHECK-NEXT: mtvsrd 35, 5
; CHECK-NEXT: mtvsrd 36, 7
; CHECK-NEXT: addi 4, 1, 96
; CHECK-NEXT: vmrghh 2, 3, 2
; CHECK-NEXT: mtvsrd 35, 6
; CHECK-NEXT: mtvsrd 37, 9
; CHECK-NEXT: addi 5, 1, 104
; CHECK-NEXT: vmrghh 3, 4, 3
; CHECK-NEXT: mtvsrd 36, 8
; CHECK-NEXT: vmrghh 4, 5, 4
; CHECK-NEXT: mtvsrd 37, 10
; CHECK-NEXT: vmrglw 2, 3, 2
; CHECK-NEXT: lxsihzx 35, 0, 4
; CHECK-NEXT: addi 4, 1, 112
; CHECK-NEXT: vmrghh 3, 3, 5
; CHECK-NEXT: vmrglw 3, 3, 4
; CHECK-NEXT: xxmrgld 0, 35, 34
; CHECK-NEXT: lxsihzx 34, 0, 5
; CHECK-NEXT: lxsihzx 35, 0, 4
; CHECK-NEXT: addi 4, 1, 120
; CHECK-NEXT: addi 5, 1, 128
; CHECK-NEXT: lxsihzx 36, 0, 5
; CHECK-NEXT: addi 5, 1, 144
; CHECK-NEXT: vmrghh 2, 3, 2
; CHECK-NEXT: lxsihzx 35, 0, 4
; CHECK-NEXT: addi 4, 1, 136
; CHECK-NEXT: vmrghh 3, 4, 3
; CHECK-NEXT: lxsihzx 36, 0, 5
; CHECK-NEXT: addi 5, 1, 152
; CHECK-NEXT: lxsihzx 37, 0, 5
; CHECK-NEXT: li 5, 7
; CHECK-NEXT: vmrglw 2, 3, 2
; CHECK-NEXT: lxsihzx 35, 0, 4
; CHECK-NEXT: addis 4, 2, .LCPI20_0@toc@ha
; CHECK-NEXT: rldic 5, 5, 57, 4
; CHECK-NEXT: addi 4, 4, .LCPI20_0@toc@l
; CHECK-NEXT: vmrghh 3, 4, 3
; CHECK-NEXT: lxv 36, 0(4)
; CHECK-NEXT: addis 4, 2, .LCPI20_1@toc@ha
; CHECK-NEXT: addi 4, 4, .LCPI20_1@toc@l
; CHECK-NEXT: vperm 3, 5, 3, 4
; CHECK-NEXT: lxv 36, 0(4)
; CHECK-NEXT: addi 4, 3, 16
; CHECK-NEXT: vperm 2, 3, 2, 4
; CHECK-NEXT: stxvl 34, 4, 5
; CHECK-NEXT: li 4, 1
; CHECK-NEXT: rldic 4, 4, 60, 3
; CHECK-NEXT: stxvl 0, 3, 4
; CHECK-NEXT: blr
call void @llvm.vp.store.v15i16(<15 x i16> %val, <15 x i16>* %ptr, <15 x i1> undef, i32 %evl)
ret void
}
declare void @llvm.vp.store.v15i16(<15 x i16>, <15 x i16>*, <15 x i1>, i32)
define <15 x i16> @load_vl_v15i16_i32(<15 x i16>* %ptr, i32 %evl) {
; CHECK-LABEL: load_vl_v15i16_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li 5, 1
; CHECK-NEXT: rldic 5, 5, 60, 3
; CHECK-NEXT: lxvl 0, 4, 5
; CHECK-NEXT: li 5, 7
; CHECK-NEXT: addi 4, 4, 16
; CHECK-NEXT: rldic 5, 5, 57, 4
; CHECK-NEXT: lxvl 34, 4, 5
; CHECK-NEXT: li 4, 24
; CHECK-NEXT: vsldoi 3, 2, 2, 12
; CHECK-NEXT: stxsiwx 34, 3, 4
; CHECK-NEXT: li 4, 28
; CHECK-NEXT: stxsihx 35, 3, 4
; CHECK-NEXT: stxv 0, 0(3)
; CHECK-NEXT: xxswapd 0, 34
; CHECK-NEXT: stfd 0, 16(3)
; CHECK-NEXT: blr
%res = call <15 x i16> @llvm.vp.load.v15i16(<15 x i16>* %ptr, <15 x i1> undef, i32 %evl)
ret <15 x i16> %res
}
declare <15 x i16> @llvm.vp.load.v15i16(<15 x i16>*, <15 x i1>, i32)
define void @store_vl_v31i8(<31 x i8>* %ptr, <31 x i8> %val, i32 %evl) {
; CHECK-LABEL: store_vl_v31i8:
; CHECK: # %bb.0:
; CHECK-NEXT: mtvsrd 34, 4
; CHECK-NEXT: mtvsrd 35, 5
; CHECK-NEXT: mtvsrd 36, 6
; CHECK-NEXT: mtvsrd 37, 7
; CHECK-NEXT: vmrghb 2, 3, 2
; CHECK-NEXT: addi 11, 1, 104
; CHECK-NEXT: addi 4, 1, 112
; CHECK-NEXT: mtvsrd 35, 8
; CHECK-NEXT: vmrghb 4, 5, 4
; CHECK-NEXT: mtvsrd 37, 9
; CHECK-NEXT: lxsibzx 32, 0, 4
; CHECK-NEXT: addi 5, 1, 120
; CHECK-NEXT: addi 6, 1, 128
; CHECK-NEXT: lxsibzx 33, 0, 6
; CHECK-NEXT: addi 7, 1, 136
; CHECK-NEXT: addi 8, 1, 144
; CHECK-NEXT: lxsibzx 38, 0, 8
; CHECK-NEXT: vmrghb 3, 5, 3
; CHECK-NEXT: lxsibzx 37, 0, 11
; CHECK-NEXT: addi 9, 1, 152
; CHECK-NEXT: addi 4, 1, 160
; CHECK-NEXT: lxsibzx 39, 0, 4
; CHECK-NEXT: addi 6, 1, 168
; CHECK-NEXT: addi 4, 1, 176
; CHECK-NEXT: lxsibzx 40, 0, 4
; CHECK-NEXT: vmrglh 2, 4, 2
; CHECK-NEXT: mtvsrd 36, 10
; CHECK-NEXT: addi 4, 1, 200
; CHECK-NEXT: vmrghb 5, 0, 5
; CHECK-NEXT: lxsibzx 32, 0, 5
; CHECK-NEXT: addi 5, 1, 96
; CHECK-NEXT: vmrghb 0, 1, 0
; CHECK-NEXT: lxsibzx 33, 0, 7
; CHECK-NEXT: addi 7, 1, 184
; CHECK-NEXT: vmrglh 5, 0, 5
; CHECK-NEXT: vmrghb 1, 6, 1
; CHECK-NEXT: lxsibzx 38, 0, 9
; CHECK-NEXT: vmrghb 6, 7, 6
; CHECK-NEXT: lxsibzx 39, 0, 5
; CHECK-NEXT: addi 5, 1, 192
; CHECK-NEXT: lxsibzx 41, 0, 5
; CHECK-NEXT: addi 5, 1, 208
; CHECK-NEXT: vmrglh 0, 6, 1
; CHECK-NEXT: lxsibzx 42, 0, 5
; CHECK-NEXT: addi 5, 1, 224
; CHECK-NEXT: vmrghb 4, 7, 4
; CHECK-NEXT: lxsibzx 39, 0, 6
; CHECK-NEXT: vmrglw 5, 0, 5
; CHECK-NEXT: vmrglh 3, 4, 3
; CHECK-NEXT: vmrghb 7, 8, 7
; CHECK-NEXT: lxsibzx 40, 0, 7
; CHECK-NEXT: vmrglw 2, 3, 2
; CHECK-NEXT: lxsibzx 35, 0, 5
; CHECK-NEXT: addi 5, 1, 240
; CHECK-NEXT: xxmrgld 0, 37, 34
; CHECK-NEXT: vmrghb 8, 9, 8
; CHECK-NEXT: lxsibzx 41, 0, 4
; CHECK-NEXT: addi 4, 1, 216
; CHECK-NEXT: lxsibzx 34, 0, 4
; CHECK-NEXT: addi 4, 1, 232
; CHECK-NEXT: vmrglh 4, 8, 7
; CHECK-NEXT: vmrghb 9, 10, 9
; CHECK-NEXT: vmrghb 2, 3, 2
; CHECK-NEXT: lxsibzx 35, 0, 4
; CHECK-NEXT: addi 4, 1, 248
; CHECK-NEXT: vmrglh 2, 2, 9
; CHECK-NEXT: vmrglw 2, 2, 4
; CHECK-NEXT: lxsibzx 36, 0, 5
; CHECK-NEXT: addi 5, 1, 256
; CHECK-NEXT: lxsibzx 37, 0, 5
; CHECK-NEXT: addi 5, 1, 272
; CHECK-NEXT: vmrghb 3, 4, 3
; CHECK-NEXT: lxsibzx 36, 0, 4
; CHECK-NEXT: addi 4, 1, 264
; CHECK-NEXT: vmrghb 4, 5, 4
; CHECK-NEXT: lxsibzx 37, 0, 5
; CHECK-NEXT: addi 5, 1, 280
; CHECK-NEXT: lxsibzx 32, 0, 5
; CHECK-NEXT: li 5, 15
; CHECK-NEXT: vmrglh 3, 4, 3
; CHECK-NEXT: lxsibzx 36, 0, 4
; CHECK-NEXT: addis 4, 2, .LCPI22_0@toc@ha
; CHECK-NEXT: rldic 5, 5, 56, 4
; CHECK-NEXT: addi 4, 4, .LCPI22_0@toc@l
; CHECK-NEXT: vmrghb 4, 5, 4
; CHECK-NEXT: lxv 37, 0(4)
; CHECK-NEXT: addis 4, 2, .LCPI22_1@toc@ha
; CHECK-NEXT: addi 4, 4, .LCPI22_1@toc@l
; CHECK-NEXT: vperm 4, 0, 4, 5
; CHECK-NEXT: vmrglw 3, 4, 3
; CHECK-NEXT: lxv 36, 0(4)
; CHECK-NEXT: addi 4, 3, 16
; CHECK-NEXT: vperm 2, 3, 2, 4
; CHECK-NEXT: stxvl 34, 4, 5
; CHECK-NEXT: li 4, 1
; CHECK-NEXT: rldic 4, 4, 60, 3
; CHECK-NEXT: stxvl 0, 3, 4
; CHECK-NEXT: blr
call void @llvm.vp.store.v31i8(<31 x i8> %val, <31 x i8>* %ptr, <31 x i1> undef, i32 %evl)
ret void
}
declare void @llvm.vp.store.v31i8(<31 x i8>, <31 x i8>*, <31 x i1>, i32)
define <31 x i8> @load_vl_v31i8_i32(<31 x i8>* %ptr, i32 %evl) {
; CHECK-LABEL: load_vl_v31i8_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li 5, 1
; CHECK-NEXT: rldic 5, 5, 60, 3
; CHECK-NEXT: lxvl 0, 4, 5
; CHECK-NEXT: li 5, 15
; CHECK-NEXT: addi 4, 4, 16
; CHECK-NEXT: rldic 5, 5, 56, 4
; CHECK-NEXT: lxvl 34, 4, 5
; CHECK-NEXT: li 4, 24
; CHECK-NEXT: vsldoi 3, 2, 2, 10
; CHECK-NEXT: stxsiwx 34, 3, 4
; CHECK-NEXT: li 4, 30
; CHECK-NEXT: stxsibx 35, 3, 4
; CHECK-NEXT: vsldoi 3, 2, 2, 12
; CHECK-NEXT: li 4, 28
; CHECK-NEXT: stxsihx 35, 3, 4
; CHECK-NEXT: stxv 0, 0(3)
; CHECK-NEXT: xxswapd 0, 34
; CHECK-NEXT: stfd 0, 16(3)
; CHECK-NEXT: blr
%res = call <31 x i8> @llvm.vp.load.v31i8(<31 x i8>* %ptr, <31 x i1> undef, i32 %evl)
ret <31 x i8> %res
}
declare <31 x i8> @llvm.vp.load.v31i8(<31 x i8>*, <31 x i1>, i32)
define void @store_vl_v3i32(<3 x i32>* %ptr, <3 x i32> %val, i32 %evl) {
; CHECK-LABEL: store_vl_v3i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 3
; CHECK-NEXT: rldic 4, 4, 58, 4
; CHECK-NEXT: stxvl 34, 3, 4
; CHECK-NEXT: blr
call void @llvm.vp.store.v3i32(<3 x i32> %val, <3 x i32>* %ptr, <3 x i1> undef, i32 %evl)
ret void
}
declare void @llvm.vp.store.v3i32(<3 x i32>, <3 x i32>*, <3 x i1>, i32)
define <3 x i32> @load_vl_v3i32_i32(<3 x i32>* %ptr, i32 %evl) {
; CHECK-LABEL: load_vl_v3i32_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 3
; CHECK-NEXT: rldic 4, 4, 58, 4
; CHECK-NEXT: lxvl 34, 3, 4
; CHECK-NEXT: blr
%res = call <3 x i32> @llvm.vp.load.v3i32(<3 x i32>* %ptr, <3 x i1> undef, i32 %evl)
ret <3 x i32> %res
}
declare <3 x i32> @llvm.vp.load.v3i32(<3 x i32>*, <3 x i1>, i32)
define void @store_vl_v7i16(<7 x i16>* %ptr, <7 x i16> %val, i32 %evl) {
; CHECK-LABEL: store_vl_v7i16:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 7
; CHECK-NEXT: rldic 4, 4, 57, 4
; CHECK-NEXT: stxvl 34, 3, 4
; CHECK-NEXT: blr
call void @llvm.vp.store.v7i16(<7 x i16> %val, <7 x i16>* %ptr, <7 x i1> undef, i32 %evl)
ret void
}
declare void @llvm.vp.store.v7i16(<7 x i16>, <7 x i16>*, <7 x i1>, i32)
define <7 x i16> @load_vl_v7i16_i32(<7 x i16>* %ptr, i32 %evl) {
; CHECK-LABEL: load_vl_v7i16_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 7
; CHECK-NEXT: rldic 4, 4, 57, 4
; CHECK-NEXT: lxvl 34, 3, 4
; CHECK-NEXT: blr
%res = call <7 x i16> @llvm.vp.load.v7i16(<7 x i16>* %ptr, <7 x i1> undef, i32 %evl)
ret <7 x i16> %res
}
declare <7 x i16> @llvm.vp.load.v7i16(<7 x i16>*, <7 x i1>, i32)
define void @store_vl_v15i8(<15 x i8>* %ptr, <15 x i8> %val, i32 %evl) {
; CHECK-LABEL: store_vl_v15i8:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 15
; CHECK-NEXT: rldic 4, 4, 56, 4
; CHECK-NEXT: stxvl 34, 3, 4
; CHECK-NEXT: blr
call void @llvm.vp.store.v15i8(<15 x i8> %val, <15 x i8>* %ptr, <15 x i1> undef, i32 %evl)
ret void
}
declare void @llvm.vp.store.v15i8(<15 x i8>, <15 x i8>*, <15 x i1>, i32)
define <15 x i8> @load_vl_v15i8_i32(<15 x i8>* %ptr, i32 %evl) {
; CHECK-LABEL: load_vl_v15i8_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 15
; CHECK-NEXT: rldic 4, 4, 56, 4
; CHECK-NEXT: lxvl 34, 3, 4
; CHECK-NEXT: blr
%res = call <15 x i8> @llvm.vp.load.v15i8(<15 x i8>* %ptr, <15 x i1> undef, i32 %evl)
ret <15 x i8> %res
}
declare <15 x i8> @llvm.vp.load.v15i8(<15 x i8>*, <15 x i1>, i32)