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Differential D109379 Diff 372051 llvm/lib/Target/PowerPC/PPCInstrVSX.td

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llvm/lib/Target/PowerPC/PPCInstrVSX.td

Show First 20 Lines • Show All 2,428 Lines • ▼ Show 20 Linesdef DblwdCmp {
dag MRGSGT = (v2i64 (XXPERMDI (v2i64 (XXSPLTW SGTWOR, 0)), dag MRGSGT = (v2i64 (XXPERMDI (v2i64 (XXSPLTW SGTWOR, 0)),
(v2i64 (XXSPLTW SGTWOR, 2)), 0)); (v2i64 (XXSPLTW SGTWOR, 2)), 0));
dag MRGUGT = (v2i64 (XXPERMDI (v2i64 (XXSPLTW UGTWOR, 0)), dag MRGUGT = (v2i64 (XXPERMDI (v2i64 (XXSPLTW UGTWOR, 0)),
(v2i64 (XXSPLTW UGTWOR, 2)), 0)); (v2i64 (XXSPLTW UGTWOR, 2)), 0));
dag MRGEQ = (v2i64 (XXPERMDI (v2i64 (XXSPLTW EQWSHAND, 0)), dag MRGEQ = (v2i64 (XXPERMDI (v2i64 (XXSPLTW EQWSHAND, 0)),
(v2i64 (XXSPLTW EQWSHAND, 2)), 0)); (v2i64 (XXSPLTW EQWSHAND, 2)), 0));
} }
def SDTVPLoad: SDTypeProfile<1, 4, [
nemanjaiUnsubmitted
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Why are these here? These nodes are target independent so it definitely seems like the wrong thing to do to define them in a PPC-specific file.

nemanjai: Why are these here? These nodes are target independent so it definitely seems like the wrong…
SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2>, SDTCisSameNumEltsAs<0, 3>, SDTCisInt<3>, SDTCisInt<4>
]>;
def SDTVPStore: SDTypeProfile<0, 5, [
SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2>, SDTCisSameNumEltsAs<0, 3>, SDTCisInt<3>, SDTCisInt<4>
]>;
def vp_load : SDNode<"ISD::VP_LOAD", SDTVPLoad,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def vp_store : SDNode<"ISD::VP_STORE", SDTVPStore,
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
def load_vl : PatFrags<(ops node:$src1, node:$src2), [
(vp_load node:$src1, undef, undef, node:$src2),
(vp_load node:$src1, undef, immAllZerosV, node:$src2)
], [{
return !cast<VPLoadSDNode>(N)->isExpandingLoad() &&
cast<VPLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD &&
cast<VPLoadSDNode>(N)->isUnindexed();
}]>;
def store_vl : PatFrags<(ops node:$src1, node:$src2, node:$src3), [
(vp_store node:$src1, node:$src2, undef, undef, node:$src3),
(vp_store node:$src1, node:$src2, undef, immAllZerosV, node:$src3)
], [{
return !cast<VPStoreSDNode>(N)->isTruncatingStore() &&
cast<VPStoreSDNode>(N)->isUnindexed();
}]>;
//---------------------------- Anonymous Patterns ----------------------------// //---------------------------- Anonymous Patterns ----------------------------//
// Predicate combinations are kept in roughly chronological order in terms of // Predicate combinations are kept in roughly chronological order in terms of
// instruction availability in the architecture. For example, VSX came in with // instruction availability in the architecture. For example, VSX came in with
// ISA 2.06 (Power7). There have since been additions in ISA 2.07 (Power8) and // ISA 2.06 (Power7). There have since been additions in ISA 2.07 (Power8) and
// ISA 3.0 (Power9). However, the granularity of features on later subtargets // ISA 3.0 (Power9). However, the granularity of features on later subtargets
// is finer for various reasons. For example, we have Power8Vector, // is finer for various reasons. For example, we have Power8Vector,
// Power8Altivec, DirectMove that all came in with ISA 2.07. The situation is // Power8Altivec, DirectMove that all came in with ISA 2.07. The situation is
// similar with ISA 3.0 with Power9Vector, Power9Altivec, IsISA3_0. Then there // similar with ISA 3.0 with Power9Vector, Power9Altivec, IsISA3_0. Then there
▲ Show 20 Lines • Show All 1,411 Lines • ▼ Show 20 Linesdef : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, DQForm:$dst),
(STXV $rS, memrix16:$dst)>; (STXV $rS, memrix16:$dst)>;
def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, DQForm:$dst), def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, DQForm:$dst),
(STXV $rS, memrix16:$dst)>; (STXV $rS, memrix16:$dst)>;
def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, XForm:$dst), def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, XForm:$dst),
(STXVX $rS, XForm:$dst)>; (STXVX $rS, XForm:$dst)>;
def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, XForm:$dst), def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, XForm:$dst),
(STXVX $rS, XForm:$dst)>; (STXVX $rS, XForm:$dst)>;
// ld/st-with-length patterns
foreach vt = [ v2i64, v4i32, v2f64, v4f32, ] in {
def : Pat<(!cast<ValueType>(""#vt) (load_vl addr:$src, i64:$rB)),
(LXVL $src, $rB)>;
def : Pat<(store_vl !cast<ValueType>(""#vt):$rS, addr:$dst, i64:$rB),
(STXVL $rS, $dst, $rB)>;
}
// We have to do v8i16 and v16i8 separately because they are not in VSRC.
foreach vt = [ v8i16, v16i8, ] in {
def : Pat<(!cast<ValueType>(""#vt) (load_vl addr:$src, i64:$rB)),
(COPY_TO_REGCLASS (LXVL $src, $rB), VRRC)>;
def : Pat<(store_vl !cast<ValueType>(""#vt):$rS, addr:$dst, i64:$rB),
(STXVL (COPY_TO_REGCLASS $rS, VSRC), $dst, $rB)>;
}
// Build vectors from i8 loads // Build vectors from i8 loads
defm : ScalToVecWPermute<v8i16, ScalarLoads.ZELi8, defm : ScalToVecWPermute<v8i16, ScalarLoads.ZELi8,
(VSPLTHs 3, (LXSIBZX ForceXForm:$src)), (VSPLTHs 3, (LXSIBZX ForceXForm:$src)),
(SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>; (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>;
defm : ScalToVecWPermute<v4i32, ScalarLoads.ZELi8, defm : ScalToVecWPermute<v4i32, ScalarLoads.ZELi8,
(XXSPLTWs (LXSIBZX ForceXForm:$src), 1), (XXSPLTWs (LXSIBZX ForceXForm:$src), 1),
(SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>; (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>;
defm : ScalToVecWPermute<v2i64, ScalarLoads.ZELi8i64, defm : ScalToVecWPermute<v2i64, ScalarLoads.ZELi8i64,
▲ Show 20 Lines • Show All 1,146 Lines • Show Last 20 Lines