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Differential D109419 Diff 371476 llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

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llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

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struct ShiftOfShiftedLogic {		struct ShiftOfShiftedLogic {
MachineInstr *Logic;		MachineInstr *Logic;
MachineInstr *Shift2;		MachineInstr *Shift2;
Register LogicNonShiftReg;		Register LogicNonShiftReg;
uint64_t ValSum;		uint64_t ValSum;
};		};

using BuildFnTy = std::function<void(MachineIRBuilder &)>;		using BuildFnTy = std::function<void(MachineIRBuilder &)>;

		struct MergeTruncStoresInfo {
		SmallVector<GStore *> FoundStores;
		GStore *LowestIdxStore = nullptr;
		Register WideSrcVal;
		arsenmUnsubmitted Not Done Reply Inline Actions Reverse the order of the fields? arsenm: Reverse the order of the fields?
		aemersonAuthorUnsubmitted Done Reply Inline Actions Why? aemerson: Why?
		arsenmUnsubmitted Not Done Reply Inline Actions They're currently ordered to maximize padding. I also don't think the NeedBSwap and NeedRotate would be the most important fields (also they should get default initializers) arsenm: They're currently ordered to maximize padding. I also don't think the NeedBSwap and NeedRotate…
		bool NeedBSwap = false;
		bool NeedRotate = false;
		};
		paquetteUnsubmitted Not Done Reply Inline Actions Looks like this part isn't used in the change? paquette: Looks like this part isn't used in the change?
		aemersonAuthorUnsubmitted Done Reply Inline Actions Yeah I initially used it but then changed it later. I'll commit this as a separate NFC change. aemerson: Yeah I initially used it but then changed it later. I'll commit this as a separate NFC change.

using OperandBuildSteps =		using OperandBuildSteps =
SmallVector<std::function<void(MachineInstrBuilder &)>, 4>;		SmallVector<std::function<void(MachineInstrBuilder &)>, 4>;
struct InstructionBuildSteps {		struct InstructionBuildSteps {
unsigned Opcode = 0; /// The opcode for the produced instruction.		unsigned Opcode = 0; /// The opcode for the produced instruction.
OperandBuildSteps OperandFns; /// Operands to be added to the instruction.		OperandBuildSteps OperandFns; /// Operands to be added to the instruction.
InstructionBuildSteps() = default;		InstructionBuildSteps() = default;
InstructionBuildSteps(unsigned Opcode, const OperandBuildSteps &OperandFns)		InstructionBuildSteps(unsigned Opcode, const OperandBuildSteps &OperandFns)
: Opcode(Opcode), OperandFns(OperandFns) {}		: Opcode(Opcode), OperandFns(OperandFns) {}
▲ Show 20 Lines • Show All 433 Lines • ▼ Show 20 Lines	public:
/// sN *a = ...		/// sN *a = ...
/// sM val = a[0] \| (a[1] << N) \| (a[2] << 2N) \| (a[3] << 3N) ...		/// sM val = a[0] \| (a[1] << N) \| (a[2] << 2N) \| (a[3] << 3N) ...
/// \endcode		/// \endcode
///		///
/// And check if the tree can be replaced with a M-bit load + possibly a		/// And check if the tree can be replaced with a M-bit load + possibly a
/// bswap.		/// bswap.
bool matchLoadOrCombine(MachineInstr &MI, BuildFnTy &MatchInfo);		bool matchLoadOrCombine(MachineInstr &MI, BuildFnTy &MatchInfo);

		bool matchTruncStoreMerge(MachineInstr &MI, MergeTruncStoresInfo &MatchInfo);
		void applyTruncStoreMerge(MachineInstr &MI, MergeTruncStoresInfo &MatchInfo);

bool matchExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI);		bool matchExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI);
void applyExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI);		void applyExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI);

bool matchExtractVecEltBuildVec(MachineInstr &MI, Register &Reg);		bool matchExtractVecEltBuildVec(MachineInstr &MI, Register &Reg);
void applyExtractVecEltBuildVec(MachineInstr &MI, Register &Reg);		void applyExtractVecEltBuildVec(MachineInstr &MI, Register &Reg);

bool matchExtractAllEltsFromBuildVector(		bool matchExtractAllEltsFromBuildVector(
MachineInstr &MI,		MachineInstr &MI,
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